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Subject: Re: [PATCH 1/1] perf, Add support for Xeon-Phi PMU
From: Peter Zijlstra <a.p.zijlstra@chello.nl>
To: Vince Weaver <vincent.weaver@maine.edu>
Cc: linux-kernel@vger.kernel.org, Paul Mackerras <paulus@samba.org>,
        Ingo Molnar <mingo@redhat.com>,
        Arnaldo Carvalho de Melo <acme@ghostprotocols.net>, eranian@gmail.com,
        "Meadows, Lawrence F" <lawrence.f.meadows@intel.com>,
        Cyrill Gorcunov <gorcunov@openvz.org>
Date: Tue, 25 Sep 2012 13:32:38 +0200
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On Thu, 2012-09-20 at 13:03 -0400, Vince Weaver wrote:
> One additional complication:  some of the cache events map to 
> event "0".  This causes problems because the generic events code
> assumes "0" means not-available.  I'm not sure the best way to address
> that problem. 

For all except P4 we could remap the 0 value to -2, that has all high
bits set (like the -1) which aren't used by hardware.

P4 is stuffing two registers in the 64bit config space and actually has
them all in use I think.. Cyrill?