From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755352Ab2I1EeX (ORCPT ); Fri, 28 Sep 2012 00:34:23 -0400 Received: from mga02.intel.com ([134.134.136.20]:42307 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752549Ab2I1Eb6 (ORCPT ); Fri, 28 Sep 2012 00:31:58 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.80,498,1344236400"; d="scan'208";a="215093235" From: Andi Kleen To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, a.p.zijlstra@chello.nl, eranian@google.com, acme@redhat.com, Andi Kleen Subject: [PATCH 17/31] perf, x86: Avoid checkpointed counters causing excessive TSX aborts Date: Thu, 27 Sep 2012 21:31:22 -0700 Message-Id: <1348806696-31170-18-git-send-email-andi@firstfloor.org> X-Mailer: git-send-email 1.7.7.6 In-Reply-To: <1348806696-31170-1-git-send-email-andi@firstfloor.org> References: <1348806696-31170-1-git-send-email-andi@firstfloor.org> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Andi Kleen With checkpointed counters there can be a situation where the counter is overflowing, aborts the transaction, is set back to a non overflowing checkpoint, causes interupt. The interrupt doesn't see the overflow because it has been checkpointed. This is then a spurious PMI, typically with a ugly NMI message. It can also lead to excessive aborts. Avoid this problem by: - Using the full counter width for counting counters (previous patch) - Forbid sampling for checkpointed counters. It's not too useful anyways, checkpointing is mainly for counting. - On a PMI always set back checkpointed counters to zero. Signed-off-by: Andi Kleen --- arch/x86/kernel/cpu/perf_event_intel.c | 26 +++++++++++++++++++++++++- 1 files changed, 25 insertions(+), 1 deletions(-) diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c index e302186..83ced1a 100644 --- a/arch/x86/kernel/cpu/perf_event_intel.c +++ b/arch/x86/kernel/cpu/perf_event_intel.c @@ -1079,6 +1079,17 @@ static void intel_pmu_enable_event(struct perf_event *event) int intel_pmu_save_and_restart(struct perf_event *event) { x86_perf_event_update(event); + /* + * For a checkpointed counter always reset back to 0. This + * avoids a situation where the counter overflows, aborts the + * transaction and is then set back to shortly before the + * overflow, and overflows and aborts again. + */ + if (event->attr.intx_checkpointed) { + /* No race with NMIs because the counter should not be armed */ + wrmsrl(event->hw.event_base, 0); + local64_set(&event->hw.prev_count, 0); + } return x86_perf_event_set_period(event); } @@ -1162,6 +1173,10 @@ again: x86_pmu.drain_pebs(regs); } + /* XXX move somewhere else. */ + if (cpuc->events[2] && cpuc->events[2]->attr.intx_checkpointed) + status |= (1ULL << 2); + for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) { struct perf_event *event = cpuc->events[bit]; @@ -1626,8 +1641,17 @@ static int hsw_hw_config(struct perf_event *event) return 0; if (event->attr.intx) event->hw.config |= HSW_INTX; - if (event->attr.intx_checkpointed) + if (event->attr.intx_checkpointed) { + /* + * Sampling of checkpointed events can cause situations where + * the CPU constantly aborts because of a overflow, which is + * then checkpointed back and ignored. Forbid checkpointing + * for sampling. + */ + if (is_sampling_event(event)) + return -EIO; event->hw.config |= HSW_INTX_CHECKPOINTED; + } return 0; } -- 1.7.7.6