From: Andi Kleen <andi@firstfloor.org>
To: linux-kernel@vger.kernel.org
Cc: x86@kernel.org, a.p.zijlstra@chello.nl, eranian@google.com,
acme@redhat.com, Andi Kleen <ak@linux.intel.com>
Subject: [PATCH 03/31] perf, x86: Basic Haswell PEBS support
Date: Thu, 27 Sep 2012 21:31:08 -0700 [thread overview]
Message-ID: <1348806696-31170-4-git-send-email-andi@firstfloor.org> (raw)
In-Reply-To: <1348806696-31170-1-git-send-email-andi@firstfloor.org>
From: Andi Kleen <ak@linux.intel.com>
Add basic PEBS support for Haswell.
The constraints are similar to SandyBridge with a few new events.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
---
arch/x86/kernel/cpu/perf_event.h | 2 ++
arch/x86/kernel/cpu/perf_event_intel.c | 2 +-
arch/x86/kernel/cpu/perf_event_intel_ds.c | 29 +++++++++++++++++++++++++++++
3 files changed, 32 insertions(+), 1 deletions(-)
diff --git a/arch/x86/kernel/cpu/perf_event.h b/arch/x86/kernel/cpu/perf_event.h
index a135a5a..8200c69 100644
--- a/arch/x86/kernel/cpu/perf_event.h
+++ b/arch/x86/kernel/cpu/perf_event.h
@@ -593,6 +593,8 @@ extern struct event_constraint intel_westmere_pebs_event_constraints[];
extern struct event_constraint intel_snb_pebs_event_constraints[];
+extern struct event_constraint intel_hsw_pebs_event_constraints[];
+
struct event_constraint *intel_pebs_constraints(struct perf_event *event);
void intel_pmu_pebs_enable(struct perf_event *event);
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index 82bae24..695abd1 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -2094,7 +2094,7 @@ __init int intel_pmu_init(void)
intel_pmu_lbr_init_nhm();
x86_pmu.event_constraints = intel_hsw_event_constraints;
-
+ x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
x86_pmu.extra_regs = intel_snb_extra_regs;
/* all extra regs are per-cpu when HT is on */
x86_pmu.er_flags |= ERF_HAS_RSP_1;
diff --git a/arch/x86/kernel/cpu/perf_event_intel_ds.c b/arch/x86/kernel/cpu/perf_event_intel_ds.c
index c8ab670..994156f 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_ds.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c
@@ -413,6 +413,35 @@ struct event_constraint intel_snb_pebs_event_constraints[] = {
EVENT_CONSTRAINT_END
};
+struct event_constraint intel_hsw_pebs_event_constraints[] = {
+ INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
+ INTEL_UEVENT_CONSTRAINT(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
+ INTEL_UEVENT_CONSTRAINT(0x02c2, 0xf), /* UOPS_RETIRED.RETIRE_SLOTS */
+ INTEL_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
+ INTEL_EVENT_CONSTRAINT(0x01c5, 0xf), /* BR_MISP_RETIRED.CONDITIONAL */
+ INTEL_EVENT_CONSTRAINT(0x04c5, 0xf), /* BR_MISP_RETIRED.ALL_BRANCHES */
+ INTEL_EVENT_CONSTRAINT(0x20c5, 0xf), /* BR_MISP_RETIRED.NEAR_TAKEN */
+ INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.* */
+ INTEL_UEVENT_CONSTRAINT(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
+ INTEL_UEVENT_CONSTRAINT(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
+ INTEL_UEVENT_CONSTRAINT(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
+ INTEL_UEVENT_CONSTRAINT(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
+ INTEL_UEVENT_CONSTRAINT(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */
+ INTEL_UEVENT_CONSTRAINT(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
+ INTEL_UEVENT_CONSTRAINT(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
+ INTEL_UEVENT_CONSTRAINT(0x01d1, 0xf), /* MEM_LOAD_UOPS_RETIRED.L1_HIT */
+ INTEL_UEVENT_CONSTRAINT(0x02d1, 0xf), /* MEM_LOAD_UOPS_RETIRED.L2_HIT */
+ INTEL_UEVENT_CONSTRAINT(0x04d1, 0xf), /* MEM_LOAD_UOPS_RETIRED.L3_HIT */
+ INTEL_UEVENT_CONSTRAINT(0x40d1, 0xf), /* MEM_LOAD_UOPS_RETIRED.HIT_LFB */
+ INTEL_UEVENT_CONSTRAINT(0x01d2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS */
+ INTEL_UEVENT_CONSTRAINT(0x02d2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT */
+ INTEL_UEVENT_CONSTRAINT(0x02d3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM */
+ INTEL_UEVENT_CONSTRAINT(0x04c8, 0xf), /* HLE_RETIRED.Abort */
+ INTEL_UEVENT_CONSTRAINT(0x04c9, 0xf), /* RTM_RETIRED.Abort */
+
+ EVENT_CONSTRAINT_END
+};
+
struct event_constraint *intel_pebs_constraints(struct perf_event *event)
{
struct event_constraint *c;
--
1.7.7.6
next prev parent reply other threads:[~2012-09-28 4:39 UTC|newest]
Thread overview: 59+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-09-28 4:31 perf PMU support for Haswell Andi Kleen
2012-09-28 4:31 ` [PATCH 01/31] perf, x86: Add PEBSv2 record support Andi Kleen
2012-09-28 8:43 ` Peter Zijlstra
2012-09-28 8:54 ` Stephane Eranian
2012-09-28 9:28 ` Peter Zijlstra
2012-09-28 11:33 ` Stephane Eranian
2012-09-28 14:42 ` Andi Kleen
2012-09-28 4:31 ` [PATCH 02/31] perf, x86: Basic Haswell PMU support Andi Kleen
2012-09-28 9:05 ` Peter Zijlstra
2012-09-28 14:58 ` Andi Kleen
[not found] ` <CABPqkBQ90Crh+EpRQq0Y+xUvrj5vzrX_=SpJQyR4p8uFR_Hr=Q@mail.gmail.com>
2012-09-28 15:21 ` Peter Zijlstra
2012-09-28 15:23 ` Andi Kleen
2012-09-28 4:31 ` Andi Kleen [this message]
2012-09-28 8:50 ` [PATCH 03/31] perf, x86: Basic Haswell PEBS support Peter Zijlstra
2012-09-28 4:31 ` [PATCH 04/31] perf, core: Add generic intx/intx_checkpointed counter modifiers Andi Kleen
2012-09-28 9:02 ` Peter Zijlstra
2012-09-28 11:35 ` Stephane Eranian
2012-09-28 14:53 ` Andi Kleen
2012-09-28 15:19 ` Peter Zijlstra
2012-09-28 15:29 ` Andi Kleen
2012-09-28 15:36 ` Peter Zijlstra
2012-09-28 15:23 ` Peter Zijlstra
2012-09-28 15:37 ` Andi Kleen
2012-09-28 4:31 ` [PATCH 05/31] perf, tools: Add :c,:t event modifiers in perf tools Andi Kleen
2012-09-28 4:31 ` [PATCH 06/31] perf, tools: Add intx/intx_checkpoint to perf script and header printing Andi Kleen
2012-09-28 4:31 ` [PATCH 07/31] perf, x86: Implement the :t and :c qualifiers for Haswell Andi Kleen
2012-09-28 4:31 ` [PATCH 08/31] perf, x86: Report PEBS event in a raw format Andi Kleen
2012-09-28 8:54 ` Peter Zijlstra
2012-09-28 8:57 ` Stephane Eranian
2012-09-28 4:31 ` [PATCH 09/31] perf, kvm: Support :t and :c perf modifiers in KVM arch perfmon emulation Andi Kleen
2012-09-28 4:31 ` [PATCH 10/31] perf, x86: Support PERF_SAMPLE_ADDR on Haswell Andi Kleen
2012-09-28 4:31 ` [PATCH 11/31] perf, x86: Support Haswell v4 LBR format Andi Kleen
2012-09-28 4:31 ` [PATCH 12/31] perf, x86: Disable LBR recording for unknown LBR_FMT Andi Kleen
2012-09-28 4:31 ` [PATCH 13/31] perf, x86: Support LBR filtering by INTX/NOTX/ABORT Andi Kleen
2012-09-28 4:31 ` [PATCH 14/31] perf, tools: Add abort,notx,intx branch filter options to perf report -j Andi Kleen
2012-09-28 4:31 ` [PATCH 15/31] perf, tools: Support sorting by intx, abort branch flags Andi Kleen
2012-09-28 4:31 ` [PATCH 16/31] perf, x86: Support full width counting on Haswell Andi Kleen
2012-09-28 4:31 ` [PATCH 17/31] perf, x86: Avoid checkpointed counters causing excessive TSX aborts Andi Kleen
2012-09-28 4:31 ` [PATCH 18/31] perf, core: Add a concept of a weightened sample Andi Kleen
2012-09-28 9:06 ` Stephane Eranian
2012-09-28 14:57 ` Andi Kleen
2012-09-28 17:09 ` Stephane Eranian
2012-09-28 4:31 ` [PATCH 19/31] perf, x86: Support weight samples for PEBS Andi Kleen
2012-09-28 4:31 ` [PATCH 20/31] perf, tools: Add support for weight Andi Kleen
2012-09-28 4:31 ` [PATCH 21/31] perf, tools: Handle XBEGIN like a jump Andi Kleen
2012-09-28 4:31 ` [PATCH 22/31] perf, core: Define generic hardware transaction events Andi Kleen
2012-09-28 9:33 ` Peter Zijlstra
2012-09-28 4:31 ` [PATCH 23/31] perf, tools: Add support for generic transaction events to perf userspace Andi Kleen
2012-09-28 4:31 ` [PATCH 24/31] perf, x86: Add the Haswell implementation of the generic transaction events Andi Kleen
2012-09-28 4:31 ` [PATCH 25/31] perf, tools: Add perf stat --transaction Andi Kleen
2012-09-28 4:31 ` [PATCH 26/31] perf, x86: Support for printing PMU state on spurious PMIs Andi Kleen
2012-09-28 9:36 ` Peter Zijlstra
2012-09-28 11:39 ` Stephane Eranian
2012-09-28 4:31 ` [PATCH 27/31] perf, core: Add generic transaction flags Andi Kleen
2012-09-28 4:31 ` [PATCH 28/31] perf, x86: Add Haswell specific transaction flag reporting Andi Kleen
2012-09-28 4:31 ` [PATCH 29/31] perf, tools: Add support for record transaction flags Andi Kleen
2012-09-28 4:31 ` [PATCH 30/31] perf, tools: Point --sort documentation to --help Andi Kleen
2012-09-28 4:31 ` [PATCH 31/31] perf, tools: Add browser support for transaction flags Andi Kleen
-- strict thread matches above, loose matches on Subject: below --
2012-10-02 23:48 perf PMU support for Haswell v2 Andi Kleen
2012-10-02 23:48 ` [PATCH 03/31] perf, x86: Basic Haswell PEBS support Andi Kleen
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1348806696-31170-4-git-send-email-andi@firstfloor.org \
--to=andi@firstfloor.org \
--cc=a.p.zijlstra@chello.nl \
--cc=acme@redhat.com \
--cc=ak@linux.intel.com \
--cc=eranian@google.com \
--cc=linux-kernel@vger.kernel.org \
--cc=x86@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).