From: Peter Zijlstra <a.p.zijlstra@chello.nl>
To: Vince Weaver <vincent.weaver@maine.edu>
Cc: linux-kernel@vger.kernel.org, Paul Mackerras <paulus@samba.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@ghostprotocols.net>,
eranian@gmail.com, "Meadows,
Lawrence F" <lawrence.f.meadows@intel.com>
Subject: Re: perf: p6 PMU working by accident, should we fix it and KNC?
Date: Fri, 19 Oct 2012 16:07:49 +0200 [thread overview]
Message-ID: <1350655669.2768.14.camel@twins> (raw)
In-Reply-To: <alpine.DEB.2.02.1210171125040.23371@vincent-weaver-1.um.maine.edu>
On Wed, 2012-10-17 at 11:35 -0400, Vince Weaver wrote:
>
> This is by accident; it looks like the code does
> val |= ARCH_PERFMON_EVENTSEL_ENABLE;
> in p6_pmu_disable_event() so that events are never truly disabled
> (is this a bug? should it be &=~ instead?).
I think that's on purpose.. from what I can remember p6 only has a
single EN bit (on PMC0) that acts for both counters. So what I did was
treat that as a global enable/disable (which it is) and did the local
enable/disable by using the NOP events.
There really might be bugs in there, its not like I use this class of
hardware very frequently (nor do anybody much it seems).
prev parent reply other threads:[~2012-10-19 14:08 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-10-17 15:35 perf: p6 PMU working by accident, should we fix it and KNC? Vince Weaver
2012-10-19 14:07 ` Peter Zijlstra [this message]
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