From: Peter Zijlstra <peterz@infradead.org>
To: Stephane Eranian <eranian@google.com>
Cc: linux-kernel@vger.kernel.org, mingo@elte.hu, ak@linux.intel.com,
acme@redhat.com, jolsa@redhat.com, ming.m.lin@intel.com
Subject: Re: [Patch v1 04/10] perf/x86: add memory profiling via PEBS Load Latency
Date: Mon, 29 Oct 2012 16:38:32 +0100 [thread overview]
Message-ID: <1351525112.24721.36.camel@twins> (raw)
In-Reply-To: <1351523752-4215-5-git-send-email-eranian@google.com>
On Mon, 2012-10-29 at 16:15 +0100, Stephane Eranian wrote:
> + fll = event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT;
> +
> perf_sample_data_init(&data, 0, event->hw.last_period);
>
> + data.period = event->hw.last_period;
> + sample_type = event->attr.sample_type;
> +
> + /*
> + * if PEBS-LL or PreciseStore
> + */
> + if (fll) {
> + if (sample_type & PERF_SAMPLE_ADDR)
> + data.addr = pebs->dla;
> +
> + /*
> + * Use latency for cost (only avail with PEBS-LL)
> + */
> + if (fll && (sample_type & PERF_SAMPLE_COST))
> + data.cost = pebs->lat;
> +
> + /*
> + * data.dsrc encodes the data source
> + */
> + if (sample_type & PERF_SAMPLE_DSRC) {
> + if (fll)
> + data.dsrc.val = load_latency_data(pebs->dse);
> + }
> + }
Why does fl1 exist? the above looks really convoluted, all fl1 checks
inside are pointless. Also 'fl1' is a bizarre name, 'pebs_ll' would be a
better name I guess.
What's wrong with:
if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT) {
if (sample_type & PERF_SAMPLE_ADDR)
data.addr = pebs->dla;
if (sample_type & PERF_SAMPLE_COST)
data.cost = perf->lat;
if (sample_type & PERF_SAMPLE_DSRC)
data.dsrc.val = load_latency_data(pebs->dse);
}
next prev parent reply other threads:[~2012-10-29 15:38 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-10-29 15:15 [Patch v1 00/10] perf: add memory access sampling support Stephane Eranian
2012-10-29 15:15 ` [Patch v1 01/10] perf/x86: improve sysfs event mapping with event string Stephane Eranian
2012-10-29 19:25 ` Andi Kleen
2012-10-29 15:15 ` [Patch v1 02/10] perf/x86: add flags to event constraints Stephane Eranian
2012-10-29 15:15 ` [Patch v1 03/10] perf: add generic memory sampling interface Stephane Eranian
2012-10-29 15:15 ` [Patch v1 04/10] perf/x86: add memory profiling via PEBS Load Latency Stephane Eranian
2012-10-29 15:23 ` Peter Zijlstra
2012-10-29 15:24 ` Stephane Eranian
2012-10-29 15:35 ` Peter Zijlstra
2012-10-29 15:39 ` Stephane Eranian
2012-10-29 15:38 ` Peter Zijlstra [this message]
2012-10-29 15:43 ` Stephane Eranian
2012-10-29 15:44 ` Peter Zijlstra
2012-10-29 19:42 ` Andi Kleen
2012-10-29 20:39 ` Stephane Eranian
2012-10-29 20:44 ` Peter Zijlstra
2012-10-29 21:16 ` Andi Kleen
2012-10-29 21:32 ` Stephane Eranian
2012-10-29 21:56 ` Andi Kleen
2012-10-30 8:43 ` Namhyung Kim
2012-10-29 15:15 ` [Patch v1 05/10] perf/x86: export PEBS load latency threshold register to sysfs Stephane Eranian
2012-10-29 15:15 ` [Patch v1 06/10] perf/x86: add support for PEBS Precise Store Stephane Eranian
2012-10-29 15:40 ` Peter Zijlstra
2012-10-29 15:44 ` Stephane Eranian
2012-10-31 5:21 ` Namhyung Kim
2012-10-31 13:28 ` Stephane Eranian
2012-10-29 15:15 ` [Patch v1 07/10] perf tools: add mem access sampling core support Stephane Eranian
2012-10-29 16:55 ` Andi Kleen
2012-10-29 17:00 ` Stephane Eranian
2012-10-31 5:51 ` Namhyung Kim
2012-10-31 13:30 ` Stephane Eranian
2012-10-29 15:15 ` [Patch v1 08/10] perf report: add support for mem access profiling Stephane Eranian
2012-10-31 6:01 ` Namhyung Kim
2012-10-29 15:15 ` [Patch v1 09/10] perf record: " Stephane Eranian
2012-10-29 15:15 ` [Patch v1 10/10] perf tools: add new mem command for memory " Stephane Eranian
2012-10-31 6:57 ` Namhyung Kim
2012-10-31 14:23 ` Stephane Eranian
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