Re: [Patch v1 04/10] perf/x86: add memory profiling via PEBS Load Latency

Stephane Eranian
2012-10-29T21:32:30Z

On Mon, Oct 29, 2012 at 10:16 PM, Andi Kleen <ak@linux.intel.com> wrote:
>> > Why do you need to replace the whole table?
>> >
>> Because I am extending them with one or two events based on cpu
>> model. That was the easiest way of doing this instead of playing
>> some kind of malloc+copy trick.
>
> I did malloc and copy.
>
>>
>> > BTW I still think my approach in the v4 Haswell patchkit
>> > is simpler and didn't rely on hardcoding these events.
>> >
>> I don't care about those events. As I found out, they are not even
>> used by perf because they are all hardcoded and that's what gets
>> used. I assume they are exposed for reference only. I don't object
>> to that. But I think the right mechanism would be one where you
>> can add events at boot time based on CPU model. It could be used
>> to add the common events as well in the common part of the init
>> code.
>
> Yes that's what I did.
>
> I don't think copying everything for everything new is a good
> approach.
>
I agree. I did that because it was the easiest thing I could think of.
Discovered I had to deal with all of this just two days ago when I
rebased. Wasn't too happy to have to deal with this at the last minute.

In any case, if you have something, then looks like I need to wait until
it's in before I can adjust this patch set.

> -Andi
>
> --
> ak@linux.intel.com -- Speaking for myself only