From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756393Ab3BEA4e (ORCPT ); Mon, 4 Feb 2013 19:56:34 -0500 Received: from mail-pa0-f53.google.com ([209.85.220.53]:63213 "EHLO mail-pa0-f53.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755486Ab3BEA4c (ORCPT ); Mon, 4 Feb 2013 19:56:32 -0500 From: Dongjin Kim Cc: Dongjin Kim , Russell King , Olof Johansson , Kukjin Kim , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] ARM: dts: Fix the timing property of MSHC controller Date: Tue, 5 Feb 2013 09:56:16 +0900 Message-Id: <1360025780-17158-1-git-send-email-tobetter@gmail.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1358959242-1667-1-git-send-email-tobetter@gmail.com> References: <1358959242-1667-1-git-send-email-tobetter@gmail.com> To: unlisted-recipients:; (no To-header on input) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This fixes the property of dw-mshc-sdr-timing and dw-mshc-ddr-timing as per its current binding, it only has two cells. Signed-off-by: Dongjin Kim --- arch/arm/boot/dts/exynos4412-odroidx.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts index f41a84e..009a9c2 100644 --- a/arch/arm/boot/dts/exynos4412-odroidx.dts +++ b/arch/arm/boot/dts/exynos4412-odroidx.dts @@ -49,8 +49,8 @@ fifo-depth = <0x80>; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3 3>; - samsung,dw-mshc-ddr-timing = <1 2 3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; slot@0 { reg = <0>; -- 1.7.10.4