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From: Peter De Schrijver <pdeschrijver@nvidia.com>
To: <pdeschrijver@nvidia.com>
Cc: Stephen Warren <swarren@nvidia.com>,
	Mike Turquette <mturquette@linaro.org>,
	Prashant Gaikwad <pgaikwad@nvidia.com>,
	<linux-kernel@vger.kernel.org>
Subject: [PATCH v6 06/10] clk: tegra: Workaround for Tegra114 MSENC problem
Date: Fri, 8 Feb 2013 15:36:38 +0200	[thread overview]
Message-ID: <1360330602-30472-7-git-send-email-pdeschrijver@nvidia.com> (raw)
In-Reply-To: <1360330602-30472-1-git-send-email-pdeschrijver@nvidia.com>

Workaround a hardware bug in MSENC during clock enable.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
 drivers/clk/tegra/clk-periph-gate.c |    9 +++++++++
 drivers/clk/tegra/clk.h             |    2 ++
 2 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/drivers/clk/tegra/clk-periph-gate.c b/drivers/clk/tegra/clk-periph-gate.c
index 6dd5332..c9083fb 100644
--- a/drivers/clk/tegra/clk-periph-gate.c
+++ b/drivers/clk/tegra/clk-periph-gate.c
@@ -43,6 +43,8 @@ static DEFINE_SPINLOCK(periph_ref_lock);
 
 #define periph_clk_to_bit(periph) (1 << (gate->clk_num % 32))
 
+#define LVL2_CLK_GATE_OVRE 0x554
+
 /* Peripheral gate clock ops */
 static int clk_periph_is_enabled(struct clk_hw *hw)
 {
@@ -83,6 +85,13 @@ static int clk_periph_enable(struct clk_hw *hw)
 		}
 	}
 
+	if (gate->flags & TEGRA_PERIPH_WAR_1005168) {
+		writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE);
+		writel_relaxed(BIT(22), gate->clk_base + LVL2_CLK_GATE_OVRE);
+		udelay(1);
+		writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE);
+	}
+
 	spin_unlock_irqrestore(&periph_ref_lock, flags);
 
 	return 0;
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 4c4bf9a..fa21c88 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -356,6 +356,7 @@ struct tegra_clk_periph_regs {
  * TEGRA_PERIPH_ON_APB - If peripheral is in the APB bus then read the
  *     bus to flush the write operation in apb bus. This flag indicates
  *     that this peripheral is in apb bus.
+ * TEGRA_PERIPH_WAR_1005168 - Apply workaround for Tegra114 MSENC bug
  */
 struct tegra_clk_periph_gate {
 	u32			magic;
@@ -375,6 +376,7 @@ struct tegra_clk_periph_gate {
 #define TEGRA_PERIPH_NO_RESET BIT(0)
 #define TEGRA_PERIPH_MANUAL_RESET BIT(1)
 #define TEGRA_PERIPH_ON_APB BIT(2)
+#define TEGRA_PERIPH_WAR_1005168 BIT(3)
 
 void tegra_periph_reset(struct tegra_clk_periph_gate *gate, bool assert);
 extern const struct clk_ops tegra_clk_periph_gate_ops;
-- 
1.7.1


  parent reply	other threads:[~2013-02-08 13:38 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <1360330602-30472-1-git-send-email-pdeschrijver@nvidia.com>
2013-02-08 13:36 ` [PATCH v6 01/10] clk: tegra: Refactor PLL programming code Peter De Schrijver
2013-02-08 13:36 ` [PATCH v6 02/10] clk: tegra: Add TEGRA_PLL_BYPASS flag Peter De Schrijver
2013-02-08 13:36 ` [PATCH v6 03/10] clk: tegra: Add PLL post divider table Peter De Schrijver
2013-02-08 13:36 ` [PATCH v6 04/10] clk: tegra: Add new fields and PLL types for Tegra114 Peter De Schrijver
2013-02-08 13:36 ` [PATCH v6 05/10] clk: tegra: Add flags to tegra_clk_periph() Peter De Schrijver
2013-02-08 13:36 ` Peter De Schrijver [this message]
2013-02-08 13:36 ` [PATCH v6 07/10] ARM: tegra: Define Tegra114 CAR binding Peter De Schrijver
2013-02-08 13:36 ` [PATCH v6 08/10] ARM: dt: Add references to tegra_car clocks Peter De Schrijver
2013-02-08 14:03   ` Felipe Balbi
2013-02-08 17:16     ` Stephen Warren
2013-02-11 10:03     ` Peter De Schrijver
2013-02-08 13:36 ` [PATCH v6 09/10] clk: tegra: Implement clocks for Tegra114 Peter De Schrijver
2013-02-08 13:36 ` [PATCH v6 10/10] clk: tegra: devicetree match for nvidia,tegra114-car Peter De Schrijver

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