From: yqzhang <yqzhang@ucsd.edu>
To: linux-kernel@vger.kernel.org
Subject: Re: [PATCH] perf, x86: add Intel IvyBridge event scheduling constraints
Date: Mon, 25 Feb 2013 21:00:21 -0800 (PST) [thread overview]
Message-ID: <1361854821579-606450.post@n7.nabble.com> (raw)
In-Reply-To: <1361355312-3323-1-git-send-email-eranian@google.com>
Hi Stephane,
I was wondering what the differences are between
CYCLE_ACTIVITY.CYCLES_**_PENDING and CYCLE_ACTIVITY.STALLS_**_PENDING,
because I could only find following events in the SDM, which seem to be
different from the ones provided here. Correct me if I'm wrong.
A3H 01H CYCLE_ACTIVITY.CYCLES_L2_PENDING
- Cycles with pending L2 miss loads. Set Cmask=2 tocount cycle. Use only
when HTT is off
A3H 02H CYCLE_ACTIVITY.CYCLES_LDM_PENDING
- Cycles with pending memory loads. Set Cmask=2 to count cycle.
A3H 05H CYCLE_ACTIVITY.STALLS_L2_PENDING
- Number of loads missed L2. Use only when HTT is off
A3H 08H CYCLE_ACTIVITY.CYCLES_L1D_PENDING
- Cycles with pending L1 cache miss loads. SetCmask=8 to count cycle.PMC2
only
Thanks a lot!
--
View this message in context: http://linux-kernel.2935.n7.nabble.com/PATCH-perf-x86-add-Intel-IvyBridge-event-scheduling-constraints-tp604032p606450.html
Sent from the Linux Kernel mailing list archive at Nabble.com.
prev parent reply other threads:[~2013-02-26 5:00 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-02-20 10:15 [PATCH] perf, x86: add Intel IvyBridge event scheduling constraints Stephane Eranian
2013-02-20 13:58 ` [tip:perf/urgent] perf/x86: Add " tip-bot for Stephane Eranian
2013-02-20 15:43 ` [PATCH] perf, x86: add " Andi Kleen
2013-02-20 19:54 ` Stephane Eranian
2013-02-20 22:08 ` Andi Kleen
2013-02-21 10:35 ` Stephane Eranian
2013-02-26 5:00 ` yqzhang [this message]
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