From: Axel Lin <axel.lin@ingics.com>
To: MyungJoo Ham <myungjoo.ham@samsung.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>, linux-kernel@vger.kernel.org
Subject: [PATCH 2/2] PM / devfreq: exynos4_bus: Fix table entry size for exynos4x12_clkdiv_dmc1
Date: Wed, 20 Mar 2013 16:15:34 +0800 [thread overview]
Message-ID: <1363767334.3758.5.camel@phoenix> (raw)
In-Reply-To: <1363767266.3758.4.camel@phoenix>
exynos4x12_clkdiv_dmc1 contains { G2DACP, DIVC2C, DIVC2C_ACLK }, thus
set the size to 3 rather than 6.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
---
drivers/devfreq/exynos4_bus.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/devfreq/exynos4_bus.c b/drivers/devfreq/exynos4_bus.c
index 45d00d1..1deee09 100644
--- a/drivers/devfreq/exynos4_bus.c
+++ b/drivers/devfreq/exynos4_bus.c
@@ -235,7 +235,7 @@ static const unsigned int exynos4x12_clkdiv_dmc0[][6] = {
/* DMC L4: 100MHz */
{7, 1, 1, 7, 1, 1},
};
-static const unsigned int exynos4x12_clkdiv_dmc1[][6] = {
+static const unsigned int exynos4x12_clkdiv_dmc1[][3] = {
/*
* Clock divider value for following
* { G2DACP, DIVC2C, DIVC2C_ACLK }
--
1.7.9.5
prev parent reply other threads:[~2013-03-20 8:23 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-03-20 8:14 [PATCH 1/2] PM / devfreq: exynos4_bus: Constify clock divider table Axel Lin
2013-03-20 8:15 ` Axel Lin [this message]
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