[PATCH 11/15] perf, x86: Add Haswell specific transaction flag reporting

Andi Kleen
2013-04-20T19:19:54Z

In the PEBS handler report the transaction flags using the new
generic transaction flags facility. Most of them come from
the "tsx_tuning" field in PEBSv2, but the abort code is derived
from the RAX register reported in the PEBS record.

Signed-off-by: Andi Kleen <ak@linux.intel.com>
---
arch/x86/kernel/cpu/perf_event_intel_ds.c | 13 +++++++++++++
1 files changed, 13 insertions(+), 0 deletions(-)

diff --git a/arch/x86/kernel/cpu/perf_event_intel_ds.c b/arch/x86/kernel/cpu/perf_event_intel_ds.c
index 60683c4..f9bb903 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_ds.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c
@@ -812,6 +812,19 @@ static void __intel_pmu_pebs_event(struct perf_event *event,
x86_pmu.intel_cap.pebs_format >= 1)
data.addr = pebs->dla;

+ if ((event->attr.sample_type & PERF_SAMPLE_WEIGHT) &&
+ (x86_pmu.intel_cap.pebs_format >= 2) &&
+ pebs_hsw->tsx_tuning)
+ data.weight = pebs_hsw->tsx_tuning & 0xffffffff;
+
+ if ((event->attr.sample_type & PERF_SAMPLE_TRANSACTION) &&
+ x86_pmu.intel_cap.pebs_format >= 2) {
+ data.transaction = pebs_hsw->tsx_tuning >> 32;
+ if ((data.transaction & PERF_SAMPLE_TXN_TRANSACTION) &&
+ (pebs->ax & 1))
+ data.transaction |= pebs->ax & 0xff000000;
+ }
+
if (has_branch_stack(event))
data.br_stack = &cpuc->lbr_stack;

--
1.7.7.6