Re: [PATCH v2 12/15] powerpc/85xx: add time base sync support for e6500

[Scott Wood <scottwood@freescale.com>]

On 04/28/2013 04:56:34 AM, Zhao Chenhui wrote:
> On Thu, Apr 25, 2013 at 07:07:24PM -0500, Scott Wood wrote:
> > On 04/24/2013 07:28:18 PM, Zhao Chenhui wrote:
> > >On Wed, Apr 24, 2013 at 05:38:16PM -0500, Scott Wood wrote:
> > >> We shouldn't base it on CPU_FTR_SMT.  For example, e6500 doesn't
> > >> claim that feature yet, except in our SDK kernel.  That doesn't
> > >> change the topology of CPU numbering.
> > >>
> > >
> > >Then, where can I get the thread information? dts?
> > >Or, wait for upstream of the thread suppport of e6500.
> >
> > It's an inherent property of e6500 (outside of some virtualization
> > scenarios, but you wouldn't run this code under a hypervisor) that
> > you have two threads per core (whether Linux uses them or not).  Or
> > you could read TMCFG0[NTHRD] if you know you're on a chip that has
> > TMRs but aren't positive it's an e6500, but I wouldn't bother.  If
> > we do ever have such a chip, there are probably other things that
> > will need updating.
> >
> 
> But how to know that there are TMRs on a chip except by CPU_FTR_SMT.

I don't know.  I said I wouldn't bother. :-)

Just assume there are 2 threads per core on e6500.  Then you won't have  
a dependency on the threading patches, and you won't break if  
CPU_FTR_SMT gets disabled for some other reason, or if the threads are  
missing from the device tree for some reason (I've seen some people  
remove them manually in an attempt to disable threading -- I tell them  
not to when I see it, but eventually others will do it again).

-Scott