From: Hiroshi Doyu <hdoyu@nvidia.com>
To: <swarren@nvidia.com>, <will.deacon@arm.com>,
<grant.likely@linaro.org>, <thierry.reding@gmail.com>,
<swarren@wwwdotorg.org>, <galak@codeaurora.org>
Cc: Hiroshi Doyu <hdoyu@nvidia.com>, <mark.rutland@arm.com>,
<devicetree@vger.kernel.org>, <iommu@lists.linux-foundation.org>,
<linux-tegra@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<lorenzo.pieralisi@arm.com>, <linux-kernel@vger.kernel.org>
Subject: [PATCHv5 1/9] of: introduce of_property_for_earch_phandle_with_args()
Date: Tue, 19 Nov 2013 11:33:05 +0200 [thread overview]
Message-ID: <1384853593-32202-2-git-send-email-hdoyu@nvidia.com> (raw)
In-Reply-To: <1384853593-32202-1-git-send-email-hdoyu@nvidia.com>
The following pattern of code is tempting:
for (i = 0; !of_parse_phandle_with_args(np, list, cells, i, args); i++)
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
---
v5:
New patch for v5.
---
include/linux/of.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/linux/of.h b/include/linux/of.h
index 276c546..131fef5 100644
--- a/include/linux/of.h
+++ b/include/linux/of.h
@@ -613,6 +613,9 @@ static inline int of_property_read_u32(const struct device_node *np,
s; \
s = of_prop_next_string(prop, s))
+#define of_property_for_each_phandle_with_args(np, list, cells, i, args) \
+ for (i = 0; !of_parse_phandle_with_args(np, list, cells, i, args); i++)
+
#if defined(CONFIG_PROC_FS) && defined(CONFIG_PROC_DEVICETREE)
extern void proc_device_tree_add_node(struct device_node *, struct proc_dir_entry *);
extern void proc_device_tree_add_prop(struct proc_dir_entry *pde, struct property *prop);
--
1.8.1.5
next prev parent reply other threads:[~2013-11-19 9:33 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-11-19 9:33 [PATCHv5 0/9] Unifying Tegra IOMMU(SMMU) driver among Tegra SoCs Hiroshi Doyu
[not found] ` < 1384853593-32202-5-git-send-email-hdoyu@nvidia.com>
[not found] ` < 1384853593-32202-2-git-send-email-hdoyu@nvidia.com>
[not found] ` <20131121124328. 46BC1C40A2C@trevor.secretlab.ca>
[not found] ` < 1384853593-32202-3-git-send-email-hdoyu@nvidia.com>
2013-11-19 9:33 ` Hiroshi Doyu [this message]
2013-11-21 12:43 ` [PATCHv5 1/9] of: introduce of_property_for_earch_phandle_with_args() Grant Likely
2013-11-21 13:12 ` Hiroshi Doyu
2013-11-21 15:56 ` Grant Likely
2013-11-21 17:20 ` Hiroshi Doyu
2013-11-21 18:52 ` Stephen Warren
2013-11-21 21:36 ` Rob Herring
2013-11-19 9:33 ` [PATCHv5 2/9] driver/core: populate devices in order for IOMMUs Hiroshi Doyu
2013-11-19 10:25 ` Thierry Reding
2013-11-19 12:03 ` Hiroshi Doyu
2013-11-19 21:22 ` Stephen Warren
2013-11-20 3:17 ` Hiroshi Doyu
2013-11-20 13:14 ` Thierry Reding
2013-11-20 14:03 ` Hiroshi Doyu
2013-11-20 16:30 ` Stephen Warren
2013-11-21 9:01 ` Hiroshi Doyu
2013-11-21 13:15 ` Grant Likely
2013-11-21 19:04 ` Stephen Warren
2013-11-22 7:41 ` Grant Likely
2013-11-22 17:35 ` Stephen Warren
2013-11-25 17:39 ` Will Deacon
2013-11-19 9:33 ` [PATCHv5 3/9] ARM: tegra: create a DT header defining SWGROUP ID Hiroshi Doyu
2013-11-19 21:36 ` Stephen Warren
2013-11-19 9:33 ` [PATCHv5 4/9] iommu/tegra: smmu: register device to iommu dynamically Hiroshi Doyu
2013-11-19 21:39 ` Stephen Warren
2013-11-21 13:23 ` Grant Likely
2013-11-21 13:38 ` Hiroshi Doyu
2013-11-19 9:33 ` [PATCHv5 5/9] iommu/tegra: smmu: calculate ASID register offset by ID Hiroshi Doyu
2013-11-19 9:33 ` [PATCHv5 6/9] iommu/tegra: smmu: get swgroups from DT "iommus=" Hiroshi Doyu
2013-11-19 21:52 ` Stephen Warren
2013-11-19 9:33 ` [PATCHv5 7/9] iommu/tegra: smmu: allow duplicate ASID wirte Hiroshi Doyu
2013-11-19 9:33 ` [PATCHv5 8/9] iommu/tegra: smmu: Rename hwgrp -> swgroups Hiroshi Doyu
2013-11-19 9:33 ` [PATCHv5 9/9] [FOR TEST] ARM: dt: tegra30: add "iommus" binding Hiroshi Doyu
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