From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754051AbaESJY2 (ORCPT ); Mon, 19 May 2014 05:24:28 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:16222 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751790AbaESJYZ (ORCPT ); Mon, 19 May 2014 05:24:25 -0400 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Mon, 19 May 2014 02:18:38 -0700 From: Alexandre Courbot To: Ben Skeggs , Stephen Warren , Thierry Reding CC: , , , , , Thierry Reding , Alexandre Courbot Subject: [PATCH 3/5] ARM: tegra: add GK20A GPU to Tegra124 DT Date: Mon, 19 May 2014 18:24:08 +0900 Message-ID: <1400491450-19223-4-git-send-email-acourbot@nvidia.com> X-Mailer: git-send-email 1.9.2 In-Reply-To: <1400491450-19223-1-git-send-email-acourbot@nvidia.com> References: <1400491450-19223-1-git-send-email-acourbot@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Thierry Reding Add the GK20A device node to Tegra124's device tree. Signed-off-by: Thierry Reding Signed-off-by: Alexandre Courbot --- arch/arm/boot/dts/tegra124.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 6e6bc4e8185c..0bccd6af81d6 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -102,6 +102,21 @@ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; + gpu@0,57000000 { + compatible = "nvidia,gk20a"; + reg = <0x0 0x57000000 0x0 0x01000000>, + <0x0 0x58000000 0x0 0x01000000>; + interrupts = , + ; + interrupt-names = "stall", "nonstall"; + clocks = <&tegra_car TEGRA124_CLK_GPU>, + <&tegra_car TEGRA124_CLK_PLL_P_OUT5>; + clock-names = "gpu", "pll"; + resets = <&tegra_car 184>; + reset-names = "gpu"; + status = "disabled"; + }; + timer@0,60005000 { compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer"; reg = <0x0 0x60005000 0x0 0x400>; -- 1.9.2