From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752904AbaE0IM5 (ORCPT ); Tue, 27 May 2014 04:12:57 -0400 Received: from mga11.intel.com ([192.55.52.93]:52132 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752870AbaE0IMt (ORCPT ); Tue, 27 May 2014 04:12:49 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.98,917,1392192000"; d="scan'208";a="538019328" From: Jiang Liu To: Benjamin Herrenschmidt , Thomas Gleixner , Grant Likely , Ingo Molnar , "H. Peter Anvin" , "Rafael J. Wysocki" , Bjorn Helgaas , Randy Dunlap , Yinghai Lu , x86@kernel.org Cc: Jiang Liu , Konrad Rzeszutek Wilk , Andrew Morton , Tony Luck , Joerg Roedel , Paul Gortmaker , Greg Kroah-Hartman , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-acpi@vger.kernel.org Subject: [Patch V3 36/37] x86, irq, SFI: release IOAPIC pin when PCI device is disabled Date: Tue, 27 May 2014 16:08:11 +0800 Message-Id: <1401178092-1228-37-git-send-email-jiang.liu@linux.intel.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1401178092-1228-1-git-send-email-jiang.liu@linux.intel.com> References: <1401178092-1228-1-git-send-email-jiang.liu@linux.intel.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Release IOAPIC pin associated with PCI device when the PCI device is disabled. Signed-off-by: Jiang Liu --- arch/x86/pci/intel_mid_pci.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/x86/pci/intel_mid_pci.c b/arch/x86/pci/intel_mid_pci.c index 337d165c64f1..09fece368592 100644 --- a/arch/x86/pci/intel_mid_pci.c +++ b/arch/x86/pci/intel_mid_pci.c @@ -227,6 +227,12 @@ static int intel_mid_pci_irq_enable(struct pci_dev *dev) return 0; } +static void intel_mid_pci_irq_disable(struct pci_dev *dev) +{ + if (dev->irq > 0) + mp_unmap_irq(dev->irq); +} + struct pci_ops intel_mid_pci_ops = { .read = pci_read, .write = pci_write, @@ -243,6 +249,7 @@ int __init intel_mid_pci_init(void) pr_info("Intel MID platform detected, using MID PCI ops\n"); pci_mmcfg_late_init(); pcibios_enable_irq = intel_mid_pci_irq_enable; + pcibios_disable_irq = intel_mid_pci_irq_disable; pci_root_ops = intel_mid_pci_ops; pci_soc_mode = 1; /* Continue with standard init */ -- 1.7.10.4