* Re: [PATCH v2] spi/pxa2xx: fix incorrect SW mode chipselect setting for BayTrail LPSS SPI
2014-06-13 15:57 [PATCH v2] spi/pxa2xx: fix incorrect SW mode chipselect setting for BayTrail LPSS SPI Chew Chiau Ee
@ 2014-06-13 13:10 ` Mika Westerberg
2014-06-17 14:46 ` Mark Brown
1 sibling, 0 replies; 3+ messages in thread
From: Mika Westerberg @ 2014-06-13 13:10 UTC (permalink / raw)
To: Chew Chiau Ee
Cc: Eric Miao, Russell King, Haojian Zhuang, Mark Brown,
linux-arm-kernel, linux-spi, linux-kernel
On Fri, Jun 13, 2014 at 11:57:25PM +0800, Chew Chiau Ee wrote:
> From: Chew, Chiau Ee <chiau.ee.chew@intel.com>
>
> It was observed that after module removal followed by insertion,
> the SW mode chipselect is not properly set. Thus causing transfer
> failure due to incorrect CS toggling.
>
> Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH v2] spi/pxa2xx: fix incorrect SW mode chipselect setting for BayTrail LPSS SPI
@ 2014-06-13 15:57 Chew Chiau Ee
2014-06-13 13:10 ` Mika Westerberg
2014-06-17 14:46 ` Mark Brown
0 siblings, 2 replies; 3+ messages in thread
From: Chew Chiau Ee @ 2014-06-13 15:57 UTC (permalink / raw)
To: Eric Miao, Russell King, Haojian Zhuang, Mark Brown
Cc: Chew Chiau Ee, Mika Westerberg, linux-arm-kernel, linux-spi,
linux-kernel
From: Chew, Chiau Ee <chiau.ee.chew@intel.com>
It was observed that after module removal followed by insertion,
the SW mode chipselect is not properly set. Thus causing transfer
failure due to incorrect CS toggling.
Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com>
---
drivers/spi/spi-pxa2xx.c | 8 ++++++--
1 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c
index a98df7e..fe79210 100644
--- a/drivers/spi/spi-pxa2xx.c
+++ b/drivers/spi/spi-pxa2xx.c
@@ -118,6 +118,7 @@ static void lpss_ssp_setup(struct driver_data *drv_data)
*/
orig = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
+ /* Test SPI_CS_CONTROL_SW_MODE bit enabling */
value = orig | SPI_CS_CONTROL_SW_MODE;
writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL);
value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
@@ -126,10 +127,13 @@ static void lpss_ssp_setup(struct driver_data *drv_data)
goto detection_done;
}
- value &= ~SPI_CS_CONTROL_SW_MODE;
+ orig = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
+
+ /* Test SPI_CS_CONTROL_SW_MODE bit disabling */
+ value = orig & ~SPI_CS_CONTROL_SW_MODE;
writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL);
value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
- if (value != orig) {
+ if (value != (orig & ~SPI_CS_CONTROL_SW_MODE)) {
offset = 0x800;
goto detection_done;
}
--
1.7.4.4
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH v2] spi/pxa2xx: fix incorrect SW mode chipselect setting for BayTrail LPSS SPI
2014-06-13 15:57 [PATCH v2] spi/pxa2xx: fix incorrect SW mode chipselect setting for BayTrail LPSS SPI Chew Chiau Ee
2014-06-13 13:10 ` Mika Westerberg
@ 2014-06-17 14:46 ` Mark Brown
1 sibling, 0 replies; 3+ messages in thread
From: Mark Brown @ 2014-06-17 14:46 UTC (permalink / raw)
To: Chew Chiau Ee
Cc: Eric Miao, Russell King, Haojian Zhuang, Mika Westerberg,
linux-arm-kernel, linux-spi, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 316 bytes --]
On Fri, Jun 13, 2014 at 11:57:25PM +0800, Chew Chiau Ee wrote:
> From: Chew, Chiau Ee <chiau.ee.chew@intel.com>
>
> It was observed that after module removal followed by insertion,
> the SW mode chipselect is not properly set. Thus causing transfer
> failure due to incorrect CS toggling.
Applied, thanks.
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2014-06-17 14:47 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2014-06-13 15:57 [PATCH v2] spi/pxa2xx: fix incorrect SW mode chipselect setting for BayTrail LPSS SPI Chew Chiau Ee
2014-06-13 13:10 ` Mika Westerberg
2014-06-17 14:46 ` Mark Brown
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).