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From: Max Filippov <jcmvbkbc@gmail.com>
To: linux-xtensa@linux-xtensa.org
Cc: Chris Zankel <chris@zankel.net>, Marc Gauthier <marc@cadence.com>,
	linux-kernel@vger.kernel.org, Max Filippov <jcmvbkbc@gmail.com>
Subject: [PATCH 8/8] xtensa: support highmem in aliasing cache flushing code
Date: Tue, 22 Jul 2014 23:01:13 +0400	[thread overview]
Message-ID: <1406055673-10100-9-git-send-email-jcmvbkbc@gmail.com> (raw)
In-Reply-To: <1406055673-10100-1-git-send-email-jcmvbkbc@gmail.com>

Use __flush_invalidate_dcache_page_alias with alias set to color of the
page physical address instead of __flush_invalidate_dcache_page: this
works for high memory pages and mapping/unmapping to the TLBTEMP area is
virtually free.

Allow building configurations with aliasing cache and highmem enabled.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
---
 arch/xtensa/mm/cache.c | 16 ++++++----------
 1 file changed, 6 insertions(+), 10 deletions(-)

diff --git a/arch/xtensa/mm/cache.c b/arch/xtensa/mm/cache.c
index 96aea66..d75aa14 100644
--- a/arch/xtensa/mm/cache.c
+++ b/arch/xtensa/mm/cache.c
@@ -59,10 +59,6 @@
  *
  */
 
-#if (DCACHE_WAY_SIZE > PAGE_SIZE) && defined(CONFIG_HIGHMEM)
-#error "HIGHMEM is not supported on cores with aliasing cache."
-#endif
-
 #if (DCACHE_WAY_SIZE > PAGE_SIZE)
 static inline void kmap_invalidate_coherent(struct page *page,
 					    unsigned long vaddr)
@@ -166,7 +162,8 @@ void flush_dcache_page(struct page *page)
 		if (!alias && !mapping)
 			return;
 
-		__flush_invalidate_dcache_page((long)page_address(page));
+		virt = TLBTEMP_BASE_1 + (phys & DCACHE_ALIAS_MASK);
+		__flush_invalidate_dcache_page_alias(virt, phys);
 
 		virt = TLBTEMP_BASE_1 + (temp & DCACHE_ALIAS_MASK);
 
@@ -231,13 +228,12 @@ update_mmu_cache(struct vm_area_struct * vma, unsigned long addr, pte_t *ptep)
 #if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
 
 	if (!PageReserved(page) && test_bit(PG_arch_1, &page->flags)) {
-
-		unsigned long paddr = (unsigned long) page_address(page);
 		unsigned long phys = page_to_phys(page);
-		unsigned long tmp = TLBTEMP_BASE_1 + (addr & DCACHE_ALIAS_MASK);
-
-		__flush_invalidate_dcache_page(paddr);
+		unsigned long tmp;
 
+		tmp = TLBTEMP_BASE_1 + (phys & DCACHE_ALIAS_MASK);
+		__flush_invalidate_dcache_page_alias(tmp, phys);
+		tmp = TLBTEMP_BASE_1 + (addr & DCACHE_ALIAS_MASK);
 		__flush_invalidate_dcache_page_alias(tmp, phys);
 		__invalidate_icache_page_alias(tmp, phys);
 
-- 
1.8.1.4


      parent reply	other threads:[~2014-07-22 19:02 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-07-22 19:01 [PATCH 0/8] xtensa: highmem support on cores with aliasing cache Max Filippov
2014-07-22 19:01 ` [PATCH 1/8] xtensa: make fixmap region addressing grow with index Max Filippov
2014-07-22 19:01 ` [PATCH 2/8] xtensa: allow fixmap and kmap span more than one page table Max Filippov
2014-07-22 19:01 ` [PATCH 3/8] xtensa: fix TLBTEMP_BASE_2 region handling in fast_second_level_miss Max Filippov
2014-07-22 19:01 ` [PATCH 4/8] xtensa: implement clear_user_highpage and copy_user_highpage Max Filippov
2014-07-22 19:01 ` [PATCH 5/8] xtensa: support aliasing cache in k[un]map_atomic Max Filippov
2014-07-22 19:01 ` [PATCH 6/8] mm/highmem: make kmap cache coloring aware Max Filippov
2014-07-22 19:35   ` Leonid Yegoshin
2014-07-22 19:46     ` Max Filippov
2014-07-22 19:01 ` [PATCH 7/8] xtensa: support aliasing cache in kmap Max Filippov
2014-07-22 19:01 ` Max Filippov [this message]

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