From: Andi Kleen <andi@firstfloor.org>
To: peterz@infradead.org
Cc: linux-kernel@vger.kernel.org, mingo@kernel.org,
eranian@google.com, Andi Kleen <ak@linux.intel.com>
Subject: [PATCH 4/5] perf, x86: Add INST_RETIRED.ALL workarounds
Date: Wed, 13 Aug 2014 18:17:48 -0700 [thread overview]
Message-ID: <1407979069-7121-5-git-send-email-andi@firstfloor.org> (raw)
In-Reply-To: <1407979069-7121-1-git-send-email-andi@firstfloor.org>
From: Andi Kleen <ak@linux.intel.com>
On Broadwell INST_RETIRED.ALL cannot be used with any period
that doesn't have the lowest 6 bits cleared. And the period
should not be smaller than 128.
Add a new callback to enforce this, and set it for Broadwell.
This is erratum BDM57 and BDM11.
v2: Use correct event name in description. Use EVENT() macro.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
---
arch/x86/kernel/cpu/perf_event.c | 3 +++
arch/x86/kernel/cpu/perf_event.h | 1 +
arch/x86/kernel/cpu/perf_event_intel.c | 19 +++++++++++++++++++
3 files changed, 23 insertions(+)
diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c
index 0adc5e3..a0adf58 100644
--- a/arch/x86/kernel/cpu/perf_event.c
+++ b/arch/x86/kernel/cpu/perf_event.c
@@ -980,6 +980,9 @@ int x86_perf_event_set_period(struct perf_event *event)
if (left > x86_pmu.max_period)
left = x86_pmu.max_period;
+ if (x86_pmu.limit_period)
+ left = x86_pmu.limit_period(event, left);
+
per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
/*
diff --git a/arch/x86/kernel/cpu/perf_event.h b/arch/x86/kernel/cpu/perf_event.h
index de81627..a46e391 100644
--- a/arch/x86/kernel/cpu/perf_event.h
+++ b/arch/x86/kernel/cpu/perf_event.h
@@ -456,6 +456,7 @@ struct x86_pmu {
struct x86_pmu_quirk *quirks;
int perfctr_second_write;
bool late_ack;
+ unsigned (*limit_period)(struct perf_event *event, unsigned l);
/*
* sysfs attrs
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index 4bfb0ec..66260e1 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -2034,6 +2034,24 @@ hsw_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
return c;
}
+/*
+ * Broadwell:
+ * The INST_RETIRED.ALL period always needs to have lowest
+ * 6bits cleared (BDM57). It shall not use a period smaller
+ * than 100 (BDM11). We combine the two to enforce
+ * a min-period of 128.
+ */
+static unsigned bdw_limit_period(struct perf_event *event, unsigned left)
+{
+ if ((event->hw.config & 0xffff) ==
+ X86_CONFIG(.event=0xc0, .umask=0x01)) {
+ if (left < 128)
+ left = 128;
+ left &= ~0x3fu;
+ }
+ return left;
+}
+
PMU_FORMAT_ATTR(event, "config:0-7" );
PMU_FORMAT_ATTR(umask, "config:8-15" );
PMU_FORMAT_ATTR(edge, "config:18" );
@@ -2711,6 +2729,7 @@ __init int intel_pmu_init(void)
x86_pmu.hw_config = hsw_hw_config;
x86_pmu.get_event_constraints = hsw_get_event_constraints;
x86_pmu.cpu_events = hsw_events_attrs;
+ x86_pmu.limit_period = bdw_limit_period;
pr_cont("Broadwell events, ");
break;
--
1.9.3
next prev parent reply other threads:[~2014-08-14 1:18 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-08-14 1:17 Updated Broadwell perf patchkit Andi Kleen
2014-08-14 1:17 ` [PATCH 1/5] perf, x86: Remove incorrect model number from Haswell perf Andi Kleen
2014-08-14 1:17 ` [PATCH 2/5] perf, x86: Document all Haswell models Andi Kleen
2014-08-14 7:01 ` Peter Zijlstra
2014-08-14 15:00 ` Andi Kleen
2014-08-14 1:17 ` [PATCH 3/5] perf, x86: Add Broadwell core support Andi Kleen
2014-08-14 7:07 ` Peter Zijlstra
2014-08-14 7:32 ` Peter Zijlstra
2014-08-14 14:58 ` Andi Kleen
2014-08-14 15:10 ` Peter Zijlstra
2014-08-14 1:17 ` Andi Kleen [this message]
2014-08-14 4:46 ` [PATCH 4/5] perf, x86: Add INST_RETIRED.ALL workarounds Stephane Eranian
2014-08-14 14:30 ` Andi Kleen
2014-08-14 17:47 ` Stephane Eranian
2014-08-14 18:41 ` Andi Kleen
2014-08-15 14:31 ` Peter Zijlstra
2014-08-15 17:21 ` Andi Kleen
2014-08-14 7:10 ` Peter Zijlstra
2014-08-14 1:17 ` [PATCH 5/5] perf, x86: Use Broadwell cache event list for Haswell Andi Kleen
-- strict thread matches above, loose matches on Subject: below --
2014-08-25 22:43 Broadwell perf support Andi Kleen
2014-08-25 22:43 ` [PATCH 4/5] perf, x86: Add INST_RETIRED.ALL workarounds Andi Kleen
2014-09-01 13:41 ` Peter Zijlstra
2014-08-27 21:03 perf, x86: Updated Broadwell patchkit Andi Kleen
2014-08-27 21:03 ` [PATCH 4/5] perf, x86: Add INST_RETIRED.ALL workarounds Andi Kleen
2014-09-02 18:44 [PATCH 1/5] perf, x86: Remove incorrect model number from Haswell perf Andi Kleen
2014-09-02 18:44 ` [PATCH 4/5] perf, x86: Add INST_RETIRED.ALL workarounds Andi Kleen
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1407979069-7121-5-git-send-email-andi@firstfloor.org \
--to=andi@firstfloor.org \
--cc=ak@linux.intel.com \
--cc=eranian@google.com \
--cc=linux-kernel@vger.kernel.org \
--cc=mingo@kernel.org \
--cc=peterz@infradead.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox