From: Toshi Kani <toshi.kani@hp.com>
To: Juergen Gross <jgross@suse.com>
Cc: stefan.bader@canonical.com, linux-kernel@vger.kernel.org,
xen-devel@lists.xensource.com, konrad.wilk@oracle.com,
ville.syrjala@linux.intel.com, hpa@zytor.com, x86@kernel.org
Subject: Re: [PATCH 1/3] x86: Make page cache mode a real type
Date: Tue, 26 Aug 2014 13:44:00 -0600 [thread overview]
Message-ID: <1409082240.28990.104.camel@misato.fc.hp.com> (raw)
In-Reply-To: <1409033783-12136-2-git-send-email-jgross@suse.com>
On Tue, 2014-08-26 at 08:16 +0200, Juergen Gross wrote:
> At the moment there are a lot of places that handle setting or getting
> the page cache mode by treating the pgprot bits equal to the cache mode.
> This is only true because there are a lot of assumptions about the setup
> of the PAT MSR. Otherwise the cache type needs to get translated into
> pgprot bits and vice versa.
>
> This patch tries to prepare for that by introducing a seperate type
> for the cache mode and adding functions to translate between those and pgprot
> values.
>
> To avoid too much performance penalty the translation between cache mode
> and pgprot values is done via tables which contain the relevant information.
> Write-back cache mode is hard-wired to be 0, all other modes are configurable
> via those tables. For large pages there are translation functions as the
> PAT bit is located at different positions in the ptes of 4k and large pages.
>
> Signed-off-by: Stefan Bader <stefan.bader@canonical.com>
> Signed-off-by: Juergen Gross <jgross@suse.com>
Hi Juergen,
Thanks for the updates! A few comments below...
> @@ -73,6 +73,9 @@ void *kmap_atomic_prot_pfn(unsigned long pfn, pgprot_t prot)
> /*
> * Map 'pfn' using protections 'prot'
> */
> +#define __PAGE_KERNEL_WC (__PAGE_KERNEL | \
> + cachemode2protval(_PAGE_CACHE_MODE_WC))
> +
> void __iomem *
> iomap_atomic_prot_pfn(unsigned long pfn, pgprot_t prot)
> {
> @@ -82,12 +85,14 @@ iomap_atomic_prot_pfn(unsigned long pfn, pgprot_t prot)
> * MTRR is UC or WC. UC_MINUS gets the real intention, of the
> * user, which is "WC if the MTRR is WC, UC if you can't do that."
> */
> - if (!pat_enabled && pgprot_val(prot) == pgprot_val(PAGE_KERNEL_WC))
> - prot = PAGE_KERNEL_UC_MINUS;
> + if (!pat_enabled && pgprot_val(prot) == __PAGE_KERNEL_WC)
> + prot = __pgprot(__PAGE_KERNEL |
> + protval_pagemode(_PAGE_CACHE_MODE_UC_MINUS));
protval_pagemode() should be cachemode2protval().
> /*
> diff --git a/drivers/video/fbdev/vermilion/vermilion.c b/drivers/video/fbdev/vermilion/vermilion.c
> index 048a666..6bbc559 100644
> --- a/drivers/video/fbdev/vermilion/vermilion.c
> +++ b/drivers/video/fbdev/vermilion/vermilion.c
> @@ -1004,13 +1004,15 @@ static int vmlfb_mmap(struct fb_info *info, struct vm_area_struct *vma)
> struct vml_info *vinfo = container_of(info, struct vml_info, info);
> unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
> int ret;
> + unsigned long prot;
>
> ret = vmlfb_vram_offset(vinfo, offset);
> if (ret)
> return -EINVAL;
>
> - pgprot_val(vma->vm_page_prot) |= _PAGE_PCD;
> - pgprot_val(vma->vm_page_prot) &= ~_PAGE_PWT;
> + prot = pgprot_val(vma->vm_page_prot) & ~_PAGE_CACHE_MASK;
> + pgprot_val(vma->vm_page_prot) =
> + prot | cachemode2protval(_PAGE_CACHE_MODE_UC);
This cache mode should be _PAGE_CACHE_MODE_UC_MINUS as the original code
only sets the PCD bit.
Thanks,
-Toshi
next prev parent reply other threads:[~2014-08-26 19:54 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-08-26 6:16 [PATCH 0/3] x86: Full support of PAT Juergen Gross
2014-08-26 6:16 ` [PATCH 1/3] x86: Make page cache mode a real type Juergen Gross
2014-08-26 19:44 ` Toshi Kani [this message]
2014-08-27 4:07 ` [Xen-devel] " Juergen Gross
2014-08-26 6:16 ` [PATCH 2/3] x86: Enable PAT to use cache mode translation tables Juergen Gross
2014-08-26 19:45 ` Toshi Kani
2014-08-28 23:21 ` Toshi Kani
2014-08-29 4:08 ` Juergen Gross
2014-08-26 6:16 ` [PATCH 3/3] Support Xen pv-domains using PAT Juergen Gross
2014-08-26 10:59 ` [Xen-devel] " David Vrabel
2014-08-26 12:54 ` Juergen Gross
2014-08-26 18:48 ` [PATCH 0/3] x86: Full support of PAT Andy Lutomirski
2014-08-26 20:08 ` Toshi Kani
2014-08-26 20:23 ` Andy Lutomirski
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1409082240.28990.104.camel@misato.fc.hp.com \
--to=toshi.kani@hp.com \
--cc=hpa@zytor.com \
--cc=jgross@suse.com \
--cc=konrad.wilk@oracle.com \
--cc=linux-kernel@vger.kernel.org \
--cc=stefan.bader@canonical.com \
--cc=ville.syrjala@linux.intel.com \
--cc=x86@kernel.org \
--cc=xen-devel@lists.xensource.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox