From: Andrew Bresticker <abrestic@chromium.org>
To: Ralf Baechle <ralf@linux-mips.org>,
Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Bresticker <abrestic@chromium.org>,
Jeffrey Deans <jeffrey.deans@imgtec.com>,
Markos Chandras <markos.chandras@imgtec.com>,
Paul Burton <paul.burton@imgtec.com>,
Qais Yousef <qais.yousef@imgtec.com>,
Jonas Gorski <jogo@openwrt.org>,
John Crispin <blogic@openwrt.org>,
David Daney <ddaney.cavm@gmail.com>,
linux-mips@linux-mips.org, linux-kernel@vger.kernel.org
Subject: [PATCH 20/24] irqchip: mips-gic: Use separate edge/level irq_chips
Date: Mon, 15 Sep 2014 16:51:23 -0700 [thread overview]
Message-ID: <1410825087-5497-21-git-send-email-abrestic@chromium.org> (raw)
In-Reply-To: <1410825087-5497-1-git-send-email-abrestic@chromium.org>
GIC edge-triggered interrupts must be acknowledged by clearing the edge
detector via a write to GIC_SH_WEDGE. Create a separate edge-triggered
irq_chip with the appropriate irq_ack() callback. This also allows us
to get rid of gic_irq_flags.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
---
arch/mips/include/asm/gic.h | 1 -
drivers/irqchip/irq-mips-gic.c | 38 ++++++++++++++++++++++++--------------
2 files changed, 24 insertions(+), 15 deletions(-)
diff --git a/arch/mips/include/asm/gic.h b/arch/mips/include/asm/gic.h
index 8d1e457..f245395 100644
--- a/arch/mips/include/asm/gic.h
+++ b/arch/mips/include/asm/gic.h
@@ -345,7 +345,6 @@
extern unsigned int gic_present;
extern unsigned int gic_frequency;
extern unsigned long _gic_base;
-extern unsigned int gic_irq_flags[];
extern unsigned int gic_cpu_pin;
extern void gic_init(unsigned long gic_base_addr,
diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
index c9ba102..6682a4e 100644
--- a/drivers/irqchip/irq-mips-gic.c
+++ b/drivers/irqchip/irq-mips-gic.c
@@ -24,7 +24,6 @@
unsigned int gic_frequency;
unsigned int gic_present;
unsigned long _gic_base;
-unsigned int gic_irq_flags[GIC_NUM_INTRS];
unsigned int gic_cpu_pin;
struct gic_pcpu_mask {
@@ -44,6 +43,7 @@ static struct gic_pending_regs pending_regs[NR_CPUS];
static struct gic_intrmask_regs intrmask_regs[NR_CPUS];
static struct irq_domain *gic_irq_domain;
static int gic_shared_intrs;
+static struct irq_chip gic_level_irq_controller, gic_edge_irq_controller;
static void __gic_irq_dispatch(void);
@@ -228,11 +228,7 @@ static void gic_ack_irq(struct irq_data *d)
{
unsigned int irq = d->hwirq;
- GIC_CLR_INTR_MASK(irq);
-
- /* Clear edge detector */
- if (gic_irq_flags[irq] & GIC_TRIG_EDGE)
- GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), irq);
+ GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), irq);
}
static int gic_set_type(struct irq_data *d, unsigned int type)
@@ -275,11 +271,13 @@ static int gic_set_type(struct irq_data *d, unsigned int type)
}
if (is_edge) {
- gic_irq_flags[irq] |= GIC_TRIG_EDGE;
- __irq_set_handler_locked(d->irq, handle_edge_irq);
+ __irq_set_chip_handler_name_locked(d->irq,
+ &gic_edge_irq_controller,
+ handle_edge_irq, NULL);
} else {
- gic_irq_flags[irq] &= ~GIC_TRIG_EDGE;
- __irq_set_handler_locked(d->irq, handle_level_irq);
+ __irq_set_chip_handler_name_locked(d->irq,
+ &gic_level_irq_controller,
+ handle_level_irq, NULL);
}
return 0;
@@ -318,11 +316,23 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
}
#endif
-static struct irq_chip gic_irq_controller = {
+static struct irq_chip gic_level_irq_controller = {
+ .name = "MIPS GIC",
+ .irq_ack = gic_mask_irq,
+ .irq_mask = gic_mask_irq,
+ .irq_mask_ack = gic_mask_irq,
+ .irq_unmask = gic_unmask_irq,
+ .irq_eoi = gic_unmask_irq,
+ .irq_set_type = gic_set_type,
+#ifdef CONFIG_SMP
+ .irq_set_affinity = gic_set_affinity,
+#endif
+};
+
+static struct irq_chip gic_edge_irq_controller = {
.name = "MIPS GIC",
.irq_ack = gic_ack_irq,
.irq_mask = gic_mask_irq,
- .irq_mask_ack = gic_ack_irq,
.irq_unmask = gic_unmask_irq,
.irq_eoi = gic_unmask_irq,
.irq_set_type = gic_set_type,
@@ -433,7 +443,6 @@ static void __init gic_basic_init(int numvpes)
GIC_SET_POLARITY(i, GIC_POL_POS);
GIC_SET_TRIGGER(i, GIC_TRIG_LEVEL);
GIC_CLR_INTR_MASK(i);
- gic_irq_flags[i] = 0;
}
vpe_local_setup(numvpes);
@@ -442,7 +451,8 @@ static void __init gic_basic_init(int numvpes)
static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq,
irq_hw_number_t hw)
{
- irq_set_chip_and_handler(virq, &gic_irq_controller, handle_level_irq);
+ irq_set_chip_and_handler(virq, &gic_level_irq_controller,
+ handle_level_irq);
GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(hw)),
GIC_MAP_TO_PIN_MSK | gic_cpu_pin);
--
2.1.0.rc2.206.gedb03e5
next prev parent reply other threads:[~2014-09-15 23:52 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-09-15 23:51 [PATCH 00/24] MIPS GIC cleanup, part 1 Andrew Bresticker
2014-09-15 23:51 ` [PATCH 01/24] MIPS: Always use IRQ domains for CPU IRQs Andrew Bresticker
2014-09-15 23:51 ` [PATCH 02/24] MIPS: Rename mips_cpu_intc_init() -> mips_cpu_irq_of_init() Andrew Bresticker
2014-09-15 23:51 ` [PATCH 03/24] MIPS: Provide a generic plat_irq_dispatch Andrew Bresticker
2014-09-17 8:56 ` Qais Yousef
2014-09-17 16:36 ` Andrew Bresticker
2014-09-15 23:51 ` [PATCH 04/24] MIPS: Set vint handler when mapping CPU interrupts Andrew Bresticker
2014-09-15 23:51 ` [PATCH 05/24] MIPS: i8259: Use IRQ domains Andrew Bresticker
2014-09-15 23:51 ` [PATCH 06/24] MIPS: Add hook to get C0 performance counter interrupt Andrew Bresticker
2014-09-15 23:51 ` [PATCH 07/24] MIPS: smp-cps: Enable all hardware interrupts on secondary CPUs Andrew Bresticker
2014-09-15 23:51 ` [PATCH 08/24] MIPS: Remove gic_{enable,disable}_interrupt() Andrew Bresticker
2014-09-15 23:51 ` [PATCH 09/24] MIPS: sead3: Remove sead3-serial.c Andrew Bresticker
2014-09-15 23:51 ` [PATCH 10/24] MIPS: sead3: Do not overlap CPU/GIC IRQ ranges Andrew Bresticker
2014-09-15 23:51 ` [PATCH 11/24] MIPS: Malta: Move MSC01 interrupt base Andrew Bresticker
2014-09-15 23:51 ` [PATCH 12/24] MIPS: Move MIPS_GIC_IRQ_BASE into platform irq.h Andrew Bresticker
2014-09-15 23:51 ` [PATCH 13/24] MIPS: Move GIC to drivers/irqchip/ Andrew Bresticker
2014-09-15 23:51 ` [PATCH 14/24] irqchip: mips-gic: Implement generic irq_ack/irq_eoi callbacks Andrew Bresticker
2014-09-17 9:14 ` Qais Yousef
2014-09-17 17:14 ` Andrew Bresticker
2014-09-15 23:51 ` [PATCH 15/24] irqchip: mips-gic: Implement irq_set_type callback Andrew Bresticker
2014-09-15 23:51 ` [PATCH 16/24] irqchip: mips-gic: Fix gic_set_affinity() return value Andrew Bresticker
2014-09-15 23:51 ` [PATCH 17/24] irqchip: mips-gic: Use IRQ domains Andrew Bresticker
2014-09-15 23:51 ` [PATCH 18/24] irqchip: mips-gic: Stop using per-platform mapping tables Andrew Bresticker
2014-09-17 9:21 ` Qais Yousef
2014-09-15 23:51 ` [PATCH 19/24] irqchip: mips-gic: Probe for number of external interrupts Andrew Bresticker
2014-09-15 23:51 ` Andrew Bresticker [this message]
2014-09-17 9:24 ` [PATCH 20/24] irqchip: mips-gic: Use separate edge/level irq_chips Qais Yousef
2014-09-17 17:15 ` Andrew Bresticker
2014-09-15 23:51 ` [PATCH 21/24] irqchip: mips-gic: Support local interrupts Andrew Bresticker
2014-09-17 9:50 ` Qais Yousef
2014-09-17 17:40 ` Andrew Bresticker
2014-09-17 21:09 ` Andrew Bresticker
2014-09-18 6:57 ` Qais Yousef
2014-09-15 23:51 ` [PATCH 22/24] irqchip: mips-gic: Remove unnecessary globals Andrew Bresticker
2014-09-15 23:51 ` [PATCH 23/24] MIPS: Malta: Use generic plat_irq_dispatch Andrew Bresticker
2014-09-15 23:51 ` [PATCH 24/24] MIPS: sead3: " Andrew Bresticker
2014-09-17 10:20 ` [PATCH 00/24] MIPS GIC cleanup, part 1 Qais Yousef
2014-09-17 17:42 ` Andrew Bresticker
2014-09-18 7:08 ` Qais Yousef
2014-09-17 14:07 ` Jason Cooper
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