From: Keith Owens <kaos@ocs.com.au>
To: "Rinaldi J. Montessi" <rinaldij@adelphia.net>
Cc: linux-kernel <linux-kernel@vger.kernel.org>
Subject: Re: APIC revisited
Date: Tue, 02 Oct 2001 12:01:33 +1000 [thread overview]
Message-ID: <14109.1001988093@kao2.melbourne.sgi.com> (raw)
In-Reply-To: Your message of "Mon, 01 Oct 2001 18:56:16 -0400." <3BB8F490.4638A81E@adelphia.net>
On Mon, 01 Oct 2001 18:56:16 -0400,
"Rinaldi J. Montessi" <rinaldij@adelphia.net> wrote:
>I am of the impression that with the noapic parameter all calls are to
>be handled via CPU0, yet I am getting several errors on CPU1 as well.
noapic only affects external internal interrupts. Inter processor
interrupts (IPIs) always use the APIC bus. Ix86 SMP does a lot of
IPIs.
prev parent reply other threads:[~2001-10-02 2:01 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2001-10-01 22:56 APIC revisited Rinaldi J. Montessi
2001-10-01 22:59 ` Benjamin LaHaise
2001-10-02 2:01 ` Keith Owens [this message]
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