From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932561AbaKRVI5 (ORCPT ); Tue, 18 Nov 2014 16:08:57 -0500 Received: from mail-ie0-f177.google.com ([209.85.223.177]:48391 "EHLO mail-ie0-f177.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932524AbaKRVIy (ORCPT ); Tue, 18 Nov 2014 16:08:54 -0500 From: Alexandru M Stan To: Mike Turquette , Heiko Stuebner , Doug Anderson , addy ke Cc: Sonny Rao , Kever Yang , linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Alexandru M Stan , robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, mark.yao@rock-chips.com, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/2] clk: rockchip: add bindings for the mmc clocks Date: Tue, 18 Nov 2014 13:08:27 -0800 Message-Id: <1416344908-5975-2-git-send-email-amstan@chromium.org> X-Mailer: git-send-email 2.1.0.rc2.206.gedb03e5 In-Reply-To: <1416344908-5975-1-git-send-email-amstan@chromium.org> References: <1416344908-5975-1-git-send-email-amstan@chromium.org> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org These clocks represent the physical clocks (including phases) and they will later be used for clock phase tuning. Suggested-by: Heiko Stuebner Signed-off-by: Alexandru M Stan --- Changes in v3: None Changes in v2: None include/dt-bindings/clock/rk3288-cru.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h index 100a08c..b4e9142 100644 --- a/include/dt-bindings/clock/rk3288-cru.h +++ b/include/dt-bindings/clock/rk3288-cru.h @@ -72,6 +72,16 @@ #define SCLK_HEVC_CABAC 111 #define SCLK_HEVC_CORE 112 +#define SCLK_SDMMC_DRV 113 +#define SCLK_SDIO0_DRV 114 +#define SCLK_SDIO1_DRV 115 +#define SCLK_EMMC_DRV 116 + +#define SCLK_SDMMC_SAMPLE 117 +#define SCLK_SDIO0_SAMPLE 118 +#define SCLK_SDIO1_SAMPLE 119 +#define SCLK_EMMC_SAMPLE 120 + #define DCLK_VOP0 190 #define DCLK_VOP1 191 -- 2.1.0.rc2.206.gedb03e5