From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753233AbbBTFG0 (ORCPT ); Fri, 20 Feb 2015 00:06:26 -0500 Received: from gate.crashing.org ([63.228.1.57]:56560 "EHLO gate.crashing.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750895AbbBTFGY (ORCPT ); Fri, 20 Feb 2015 00:06:24 -0500 Message-ID: <1424408769.27448.28.camel@kernel.crashing.org> Subject: Re: Concerns about "mpt2sas: Added Reply Descriptor Post Queue (RDPQ) Array support" From: Benjamin Herrenschmidt To: Sreekanth Reddy Cc: "Martin K. Petersen" , James Bottomley , Linux Kernel Mailing List , scsi , Christoph Hellwig Date: Fri, 20 Feb 2015 16:06:09 +1100 In-Reply-To: <1424408500.27448.25.camel@kernel.crashing.org> References: <1424408500.27448.25.camel@kernel.crashing.org> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.12.7-0ubuntu1 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 2015-02-20 at 16:01 +1100, Benjamin Herrenschmidt wrote: > Hi Sreekanth ! > > While looking at some (unrelated) issue where mtp2sas seems to be using > 32-bit DMA instead of 64-bit DMA on some POWER platforms, I noticed this > patch which was merged as 5fb1bf8aaa832e1e9ca3198de7bbecb8eff7db9c. > > Can you confirm my understanding that you are: > > - Setting the DMA mask to 32-bit > > - Mapping pages for DMA > > - Changing the DMA mask to 64-bit > > ? > > If yes, then I don't think this is a legal thing to do and definitely > not something supported by all architectures. It might work by accident, > but there is no telling that any translation/DMA mapping provided before > a call to set_dma_mask() is still valid after that call. > > The architecture might have to completely reconfigure the iommu, for > example on some PowerPC platforms, we switch from a remapped mapping to > a direct linear map of all memory, all translations established before > the switch might be lost (it depends on the specific implementation). > > How does it work on x86 with DMAR ? Note that even on powerpc platforms where it would work because we maintain both 32-bit and 64-bit bypass windows in the device address space simultaneously, you will leak iommu entries unless you also switch back to 32-bit when freeing the 32-bit mappings... (and you would probably crash if you tried to free a 64-bit mapping while in 32-bit mode). The iommu APIs weren't designed with that "switching mask" facility in mind... Ben.