Re: [PATCH 3.2 12/24] MIPS: Fix C0_Pagegrain[IEC] support.

[Ben Hutchings <ben@decadent.org.uk>]

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On Tue, 2015-03-03 at 15:24 -0800, David Daney wrote:
> On 03/03/2015 02:11 PM, Ben Hutchings wrote:
> > 3.2.68-rc1 review patch.  If anyone has any objections, please let me know.
> >
> 
> I object!
> 
> Because ...
> 
> > ------------------
> >
> > From: David Daney <david.daney@cavium.com>
> >
> > commit 9ead8632bbf454cfc709b6205dc9cd8582fb0d64 upstream.
> >
> > The following commits:
> >
> >    5890f70f15c52d (MIPS: Use dedicated exception handler if CPU supports RI/XI exceptions)
> >    6575b1d4173eae (MIPS: kernel: cpu-probe: Detect unique RI/XI exceptions)
> >
> > break the kernel for *all* existing MIPS CPUs that implement the
> > CP0_PageGrain[IEC] bit.  They cause the TLB exception handlers to be
> > generated without the legacy execute-inhibit handling, but never set
> > the CP0_PageGrain[IEC] bit to activate the use of dedicated exception
> > vectors for execute-inhibit exceptions.  The result is that upon
> > detection of an execute-inhibit violation, we loop forever in the TLB
> > exception handlers instead of sending SIGSEGV to the task.
> >
> > If we are generating TLB exception handlers expecting separate
> > vectors, we must also enable the CP0_PageGrain[IEC] feature.
> >
> > The bug was introduced in kernel version 3.17.
> 
> ... I don't think the patch should be applied to versions prior to 3.17
[...]

Sorry about that - I dropped this one just before sending, but didn't
regenerate the mailbox.

Ben.

-- 
Ben Hutchings
Horngren's Observation:
                   Among economists, the real world is often a special case.

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