From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757356AbbCMQVe (ORCPT ); Fri, 13 Mar 2015 12:21:34 -0400 Received: from mail-by2on0115.outbound.protection.outlook.com ([207.46.100.115]:21881 "EHLO na01-by2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1756775AbbCMQV2 (ORCPT ); Fri, 13 Mar 2015 12:21:28 -0400 X-WSS-ID: 0NL5S3M-07-ZW7-02 X-M-MSG: From: To: CC: Joel Schopp , Tony Luck , Borislav Petkov , Thomas Gleixner , "Ingo Molnar" , "H. Peter Anvin" , , , Jesse Larrew Subject: [PATCH v2] mce: use safe MSR accesses Date: Fri, 13 Mar 2015 11:03:39 -0500 Message-ID: <1426262619-5016-1-git-send-email-jesse.larrew@amd.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 Authentication-Results: spf=none (sender IP is 165.204.84.221) smtp.mailfrom=Jesse.Larrew@amd.com; alien8.de; dkim=none (message not signed) header.d=none; X-Forefront-Antispam-Report: CIP:165.204.84.221;CTRY:US;IPV:NLI;EFV:NLI;BMV:1;SFV:NSPM;SFS:(10019020)(6009001)(428002)(189002)(199003)(50226001)(36756003)(33646002)(19580395003)(19580405001)(86152002)(50986999)(105586002)(106466001)(2351001)(229853001)(101416001)(87936001)(86362001)(77156002)(48376002)(77096005)(47776003)(50466002)(110136001)(46102003)(92566002)(53416004)(62966003);DIR:OUT;SFP:1102;SCL:1;SRVR:BN1PR0201MB0786;H:atltwp01.amd.com;FPR:;SPF:None;MLV:sfv;MX:1;A:1;LANG:en; X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BN1PR0201MB0786; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(601004)(5002009)(5005006);SRVR:BN1PR0201MB0786;BCL:0;PCL:0;RULEID:;SRVR:BN1PR0201MB0786; X-Forefront-PRVS: 05143A8241 X-OriginatorOrg: amd4.onmicrosoft.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Mar 2015 16:21:24.3164 (UTC) X-MS-Exchange-CrossTenant-Id: fde4dada-be84-483f-92cc-e026cbee8e96 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=fde4dada-be84-483f-92cc-e026cbee8e96;Ip=[165.204.84.221];Helo=[atltwp01.amd.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN1PR0201MB0786 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Jesse Larrew Certain MSRs are only relevant to a kernel in host mode, and kvm had chosen not to implement these MSRs at all for guests. If a guest kernel ever tried to access these MSRs, the result was a general protection fault. KVM will be separately patched to return 0 when these MSRs are read, and this patch ensures that MSR accesses are tolerant of exceptions. Signed-off-by: Jesse Larrew --- arch/x86/kernel/cpu/mcheck/mce.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c index 61a9668ce..2737ced 100644 --- a/arch/x86/kernel/cpu/mcheck/mce.c +++ b/arch/x86/kernel/cpu/mcheck/mce.c @@ -1540,7 +1540,7 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) if (c->x86 == 0x15 && (c->x86_model >= 0x10 && c->x86_model <= 0x1f)) { int i; - u64 val, hwcr; + u64 hwcr; bool need_toggle; u32 msrs[] = { 0x00000413, /* MC4_MISC0 */ @@ -1556,13 +1556,8 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) wrmsrl(MSR_K7_HWCR, hwcr | BIT(18)); for (i = 0; i < ARRAY_SIZE(msrs); i++) { - rdmsrl(msrs[i], val); - - /* CntP bit set? */ - if (val & BIT_64(62)) { - val &= ~BIT_64(62); - wrmsrl(msrs[i], val); - } + /* Clear CntP bit safely */ + msr_clear_bit(msrs[i], 62); } /* restore old settings */ -- 1.9.1