From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755760AbbCRPqx (ORCPT ); Wed, 18 Mar 2015 11:46:53 -0400 Received: from mail-lb0-f170.google.com ([209.85.217.170]:33646 "EHLO mail-lb0-f170.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750986AbbCRPqt (ORCPT ); Wed, 18 Mar 2015 11:46:49 -0400 From: Dmitry Osipenko To: digetx@gmail.com, Stephen Warren , Thierry Reding , Alexandre Courbot , Daniel Lezcano , Thomas Gleixner Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH] clocksource: tegra: Maintain CPU endianness Date: Wed, 18 Mar 2015 18:44:49 +0300 Message-Id: <1426693503-6056-1-git-send-email-digetx@gmail.com> X-Mailer: git-send-email 2.3.2 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Support big-endian kernel by using endian-aware register access functions. Signed-off-by: Dmitry Osipenko --- drivers/clocksource/tegra20_timer.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clocksource/tegra20_timer.c b/drivers/clocksource/tegra20_timer.c index d2616ef..d8a3a4e 100644 --- a/drivers/clocksource/tegra20_timer.c +++ b/drivers/clocksource/tegra20_timer.c @@ -57,9 +57,9 @@ static u64 persistent_ms, last_persistent_ms; static struct delay_timer tegra_delay_timer; #define timer_writel(value, reg) \ - __raw_writel(value, timer_reg_base + (reg)) + writel_relaxed(value, timer_reg_base + (reg)) #define timer_readl(reg) \ - __raw_readl(timer_reg_base + (reg)) + readl_relaxed(timer_reg_base + (reg)) static int tegra_timer_set_next_event(unsigned long cycles, struct clock_event_device *evt) -- 2.3.2