From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755212AbbCXTX3 (ORCPT ); Tue, 24 Mar 2015 15:23:29 -0400 Received: from mail-am1on0091.outbound.protection.outlook.com ([157.56.112.91]:19512 "EHLO emea01-am1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1754724AbbCXTWl (ORCPT ); Tue, 24 Mar 2015 15:22:41 -0400 From: To: , Frederic Weisbecker , Steven Rostedt , "Paul E. McKenney" , Ingo Molnar , Thomas Gleixner , Peter Zijlstra , Borislav Petkov , Li Zhong , Mike Galbraith , Kevin Hilman CC: Chris Metcalf Subject: [PATCH 3/4] nohz: add tick_nohz_full_clear_cpus() API Date: Tue, 24 Mar 2015 15:21:34 -0400 Message-ID: <1427224895-30830-4-git-send-email-cmetcalf@ezchip.com> X-Mailer: git-send-email 2.1.2 In-Reply-To: <1427224895-30830-1-git-send-email-cmetcalf@ezchip.com> References: <1427224895-30830-1-git-send-email-cmetcalf@ezchip.com> X-EOPAttributedMessage: 0 Authentication-Results: spf=softfail (sender IP is 12.216.194.146) smtp.mailfrom=cmetcalf@tilera.com; ezchip.com; dkim=none (message not signed) header.d=none; X-Forefront-Antispam-Report: CIP:12.216.194.146;CTRY:US;IPV:NLI;EFV:NLI;BMV:1;SFV:NSPM;SFS:(10009020)(6009001)(199003)(189002)(960300001)(47776003)(50466002)(77156002)(62966003)(86362001)(87936001)(86152002)(19580405001)(2950100001)(42186005)(19580395003)(50226001)(92566002)(50986999)(76176999)(105596002)(229853001)(46102003)(106466001)(48376002)(36756003)(33646002)(7059030)(921003)(1121003);DIR:OUT;SFP:1101;SCL:1;SRVR:DB3PR02MB0539;H:ld-1.internal.tilera.com;FPR:;SPF:SoftFail;MLV:sfv;A:1;MX:1;LANG:en; MIME-Version: 1.0 Content-Type: text/plain X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:DB3PR02MB0539; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(601004)(5005006)(5002010);SRVR:DB3PR02MB0539;BCL:0;PCL:0;RULEID:;SRVR:DB3PR02MB0539; X-Forefront-PRVS: 0525BB0ADF X-OriginatorOrg: ezchip.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Mar 2015 19:22:36.5929 (UTC) X-MS-Exchange-CrossTenant-Id: 0fc16e0a-3cd3-4092-8b2f-0a42cff122c3 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0fc16e0a-3cd3-4092-8b2f-0a42cff122c3;Ip=[12.216.194.146];Helo=[ld-1.internal.tilera.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB3PR02MB0539 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Chris Metcalf This is useful, for example, to modify a cpumask to avoid the nohz cores so that interrupts aren't sent to them. Signed-off-by: Chris Metcalf --- Motivated by patch 4/4 in this series. include/linux/tick.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/linux/tick.h b/include/linux/tick.h index 9c085dc12ae9..d53ad4892a39 100644 --- a/include/linux/tick.h +++ b/include/linux/tick.h @@ -186,6 +186,12 @@ static inline bool tick_nohz_full_cpu(int cpu) return cpumask_test_cpu(cpu, tick_nohz_full_mask); } +static inline void tick_nohz_full_clear_cpus(struct cpumask *mask) +{ + if (tick_nohz_full_enabled()) + cpumask_andnot(mask, mask, tick_nohz_full_mask); +} + extern void __tick_nohz_full_check(void); extern void tick_nohz_full_kick(void); extern void tick_nohz_full_kick_cpu(int cpu); @@ -194,6 +200,7 @@ extern void __tick_nohz_task_switch(struct task_struct *tsk); #else static inline bool tick_nohz_full_enabled(void) { return false; } static inline bool tick_nohz_full_cpu(int cpu) { return false; } +static inline void tick_nohz_full_clear_cpus(struct cpumask *mask) { } static inline void __tick_nohz_full_check(void) { } static inline void tick_nohz_full_kick_cpu(int cpu) { } static inline void tick_nohz_full_kick(void) { } -- 2.1.2