From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752299AbbEGW6p (ORCPT ); Thu, 7 May 2015 18:58:45 -0400 Received: from mga09.intel.com ([134.134.136.24]:56246 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751352AbbEGW4l (ORCPT ); Thu, 7 May 2015 18:56:41 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.13,386,1427785200"; d="scan'208";a="691641773" From: Andi Kleen To: peterz@infradead.org Cc: kan.liang@intel.com, eranian@google.com, acme@infradead.org, linux-kernel@vger.kernel.org Subject: perf: Add basic Skylake PMU support Date: Thu, 7 May 2015 15:56:23 -0700 Message-Id: <1431039392-12589-1-git-send-email-andi@firstfloor.org> X-Mailer: git-send-email 1.9.3 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patchkit adds support for the Intel Skylake core PMU to perf, documented in the recently released SDM 054[1] Vol3, 17.9 and 18.12. The main user visible feature is timed branch records, which allows to get cycle counts for individual basic blocks, and a time stamp for PEBS records which improves multi-record PEBS. The LBRs (branch records) also have been extended to 32, which allows more accurate branch sampling and deeper call stacks. -Andi [1] http://www.cps.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html