From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752039AbbEGW4m (ORCPT ); Thu, 7 May 2015 18:56:42 -0400 Received: from mga09.intel.com ([134.134.136.24]:56246 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750843AbbEGW4k (ORCPT ); Thu, 7 May 2015 18:56:40 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.13,386,1427785200"; d="scan'208";a="691641774" From: Andi Kleen To: peterz@infradead.org Cc: kan.liang@intel.com, eranian@google.com, acme@infradead.org, linux-kernel@vger.kernel.org, Andi Kleen Subject: [PATCH 3/9] x86: Add new MSRs and MSR bits used for Skylake perfmon Date: Thu, 7 May 2015 15:56:26 -0700 Message-Id: <1431039392-12589-4-git-send-email-andi@firstfloor.org> X-Mailer: git-send-email 1.9.3 In-Reply-To: <1431039392-12589-1-git-send-email-andi@firstfloor.org> References: <1431039392-12589-1-git-send-email-andi@firstfloor.org> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Andi Kleen Add new MSRs (LBR_INFO) and some new MSR bits used by the Skylake PMU driver. Signed-off-by: Andi Kleen --- arch/x86/include/asm/perf_event.h | 7 +++++++ arch/x86/include/uapi/asm/msr-index.h | 6 ++++++ 2 files changed, 13 insertions(+) diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h index dc0f6ed..7bcb861 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -159,6 +159,13 @@ struct x86_pmu_capability { */ #define INTEL_PMC_IDX_FIXED_BTS (INTEL_PMC_IDX_FIXED + 16) +#define GLOBAL_STATUS_COND_CHG BIT_ULL(63) +#define GLOBAL_STATUS_BUFFER_OVF BIT_ULL(62) +#define GLOBAL_STATUS_UNC_OVF BIT_ULL(61) +#define GLOBAL_STATUS_ASIF BIT_ULL(60) +#define GLOBAL_STATUS_COUNTERS_FROZEN BIT_ULL(59) +#define GLOBAL_STATUS_LBRS_FROZEN BIT_ULL(58) + /* * IBS cpuid feature detection */ diff --git a/arch/x86/include/uapi/asm/msr-index.h b/arch/x86/include/uapi/asm/msr-index.h index c469490..a6e1a2d 100644 --- a/arch/x86/include/uapi/asm/msr-index.h +++ b/arch/x86/include/uapi/asm/msr-index.h @@ -72,6 +72,12 @@ #define MSR_LBR_CORE_FROM 0x00000040 #define MSR_LBR_CORE_TO 0x00000060 +#define MSR_LBR_INFO_0 0x00000dc0 /* ... 0xddf for _31 */ +#define LBR_INFO_MISPRED (1UL << 63) +#define LBR_INFO_IN_TX (1UL << 62) +#define LBR_INFO_ABORT (1UL << 61) +#define LBR_INFO_CYCLES 0xffff + #define MSR_IA32_PEBS_ENABLE 0x000003f1 #define MSR_IA32_DS_AREA 0x00000600 #define MSR_IA32_PERF_CAPABILITIES 0x00000345 -- 1.9.3