Re: lockup when C1E and high-resolution timers enabled

Christoph Fritz
2015-06-14T04:40:07Z

On Sun, 2015-06-14 at 11:13 +0800, Daniel J Blueman wrote:
> On Sunday, June 14, 2015 at 4:00:06 AM UTC+8, Christoph Fritz wrote:
> > Hi,
> >
> > on following computer configuration, I do get hard lockup under heavy
> > IO-Load (using rsync):
> >
> > - CONFIG_HIGH_RES_TIMERS=y
> > - CPU: AMD FX(tm)-8350 Eight-Core Processor (family 0x15 model 0x2)
> > - Motherboard: 'GA-970A-UD3P (rev. 1.0)' AMD 970/SB950
> > - BIOS: C1E enabled (on 'GA-970A-UD3P' there is no disable option)
> > - Kernels: 4.1.0-rc6, 4.0.x, 3.16.x
> >
> > Tests:
> > - add kernel parameter "idle=halt" -> system runs fine
> > - disable CONFIG_HIGH_RES_TIMERS -> system runs fine
> > - change motherboard and disable C1E -> system runs fine
> > - change CPU to AMD Phenom II X6 Processor -> system runs fine
> [..]
>
> C1E disconnects HyperTransport links when all cores enter C1 (halt)
> for a period of time; this is all at the platform level, so isn't due
> to the kernel. The AMD AGESA code which controls the setup of this
> mechanism is updated in the F2g BIOS:
> http://www.gigabyte.com/products/product-page.aspx?pid=4717#bios
>
> Did you try both BIOS releases with defaults?

Yes, rechecked both versions: Same bad behaviour.

> If still issues, also try with the current family 10h microcode from
> http://www.amd64.org/microcode/amd-ucode-latest.tar.bz2

Don't you mean family 15h for 'AMD FX(tm)-8350' ?

already using latest microcode:

[ 0.514490] microcode: CPU0: patch_level=0x06000822
[ 0.514497] microcode: CPU1: patch_level=0x06000822
[ 0.514508] microcode: CPU2: patch_level=0x06000822
[ 0.514519] microcode: CPU3: patch_level=0x06000822
[ 0.514529] microcode: CPU4: patch_level=0x06000822
[ 0.514540] microcode: CPU5: patch_level=0x06000822
[ 0.514550] microcode: CPU6: patch_level=0x06000822
[ 0.514561] microcode: CPU7: patch_level=0x06000822