From: Hai Li <hali@codeaurora.org>
To: dri-devel@lists.freedesktop.org
Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
robdclark@gmail.com, Hai Li <hali@codeaurora.org>
Subject: [PATCH 0/2] drm/msm/mdp5: Refactor CTL code
Date: Fri, 26 Jun 2015 16:03:24 -0400 [thread overview]
Message-ID: <1435349006-26136-1-git-send-email-hali@codeaurora.org> (raw)
Instead of allocating CTL for each CRTC, we start to associate CTL
to each display interface, which reflects real HW requirement.
It also helps in making use of HW single FLUSH feature to sync
between dual DSI pipes.
Hai Li (2):
drm/msm/mdp5: Allocate CTL for each display interface
drm/msm/mdp5: Allocate CTL0/1 for dual DSI single FLUSH
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c | 12 +-
drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c | 26 +---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c | 179 ++++++++++++++++++------
drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.h | 13 +-
drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c | 18 ++-
drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c | 38 +++--
drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h | 8 +-
7 files changed, 200 insertions(+), 94 deletions(-)
--
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next reply other threads:[~2015-06-26 20:03 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-26 20:03 Hai Li [this message]
2015-06-26 20:03 ` [PATCH 1/2] drm/msm/mdp5: Allocate CTL for each display interface Hai Li
2015-06-26 20:03 ` [PATCH 2/2] drm/msm/mdp5: Allocate CTL0/1 for dual DSI single FLUSH Hai Li
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