[PATCH v5 5/8] clk: tegra: switch to GENMASK()

[Andy Shevchenko <andriy.shevchenko@linux.intel.com>]

Convert the code to use GENMASK() helper instead of custom approach.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 drivers/clk/tegra/clk-divider.c |  7 +++----
 drivers/clk/tegra/clk-pll.c     | 13 ++++++-------
 drivers/clk/tegra/clk-super.c   |  2 +-
 3 files changed, 10 insertions(+), 12 deletions(-)

diff --git a/drivers/clk/tegra/clk-divider.c b/drivers/clk/tegra/clk-divider.c
index 59a5714..bf7f667 100644
--- a/drivers/clk/tegra/clk-divider.c
+++ b/drivers/clk/tegra/clk-divider.c
@@ -24,9 +24,8 @@
 #include "clk.h"
 
 #define pll_out_override(p) (BIT((p->shift - 6)))
-#define div_mask(d) ((1 << (d->width)) - 1)
 #define get_mul(d) (1 << d->frac_width)
-#define get_max_div(d) div_mask(d)
+#define get_max_div(d) GENMASK(d->width - 1, 0)
 
 #define PERIPH_CLK_UART_DIV_ENB BIT(24)
 
@@ -73,7 +72,7 @@ static unsigned long clk_frac_div_recalc_rate(struct clk_hw *hw,
 	u64 rate = parent_rate;
 
 	reg = readl_relaxed(divider->reg) >> divider->shift;
-	div = reg & div_mask(divider);
+	div = reg & GENMASK(divider->width - 1, 0);
 
 	mul = get_mul(divider);
 	div += mul;
@@ -120,7 +119,7 @@ static int clk_frac_div_set_rate(struct clk_hw *hw, unsigned long rate,
 		spin_lock_irqsave(divider->lock, flags);
 
 	val = readl_relaxed(divider->reg);
-	val &= ~(div_mask(divider) << divider->shift);
+	val &= ~(GENMASK(divider->width - 1, 0) << divider->shift);
 	val |= div << divider->shift;
 
 	if (divider->flags & TEGRA_DIVIDER_UART) {
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 05c6d08..c8488b5 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -39,13 +39,13 @@
 #define PLL_MISC_DCCON_SHIFT 20
 #define PLL_MISC_CPCON_SHIFT 8
 #define PLL_MISC_CPCON_WIDTH 4
-#define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1)
+#define PLL_MISC_CPCON_MASK GENMASK(PLL_MISC_CPCON_WIDTH - 1, 0)
 #define PLL_MISC_LFCON_SHIFT 4
 #define PLL_MISC_LFCON_WIDTH 4
-#define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1)
+#define PLL_MISC_LFCON_MASK GENMASK(PLL_MISC_LFCON_WIDTH - 1, 0)
 #define PLL_MISC_VCOCON_SHIFT 0
 #define PLL_MISC_VCOCON_WIDTH 4
-#define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1)
+#define PLL_MISC_VCOCON_MASK GENMASK(PLL_MISC_VCOCON_WIDTH - 1, 0)
 
 #define OUT_OF_TABLE_CPCON 8
 
@@ -193,11 +193,10 @@
 #define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p)
 #define pll_override_writel(val, offset, p) writel(val, p->pmc + offset)
 
-#define mask(w) ((1 << (w)) - 1)
-#define divm_mask(p) mask(p->params->div_nmp->divm_width)
-#define divn_mask(p) mask(p->params->div_nmp->divn_width)
+#define divm_mask(p) GENMASK(p->params->div_nmp->divm_width - 1, 0)
+#define divn_mask(p) GENMASK(p->params->div_nmp->divn_width - 1, 0)
 #define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\
-		      mask(p->params->div_nmp->divp_width))
+		      GENMASK(p->params->div_nmp->divp_width - 1, 0))
 
 #define divm_shift(p) (p)->params->div_nmp->divm_shift
 #define divn_shift(p) (p)->params->div_nmp->divn_shift
diff --git a/drivers/clk/tegra/clk-super.c b/drivers/clk/tegra/clk-super.c
index 2fd924d..e31e741 100644
--- a/drivers/clk/tegra/clk-super.c
+++ b/drivers/clk/tegra/clk-super.c
@@ -38,7 +38,7 @@
 
 #define super_state(s) (BIT(s) << SUPER_STATE_SHIFT)
 #define super_state_to_src_shift(m, s) ((m->width * s))
-#define super_state_to_src_mask(m) (((1 << m->width) - 1))
+#define super_state_to_src_mask(m) GENMASK(m->width - 1, 0)
 
 static u8 clk_super_get_parent(struct clk_hw *hw)
 {
-- 
2.1.4