From: Toshi Kani <toshi.kani@hp.com>
To: Jan Beulich <JBeulich@suse.com>
Cc: peterz@infradead.org, mingo@kernel.org, x86@kernel.org,
tglx@linutronix.de, bp@suse.de, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] x86, pat: Add comments to cachemode translation tables
Date: Thu, 23 Jul 2015 08:27:00 -0600 [thread overview]
Message-ID: <1437661620.3214.281.camel@hp.com> (raw)
In-Reply-To: <55B0A9110200007800094558@prv-mh.provo.novell.com>
On Thu, 2015-07-23 at 00:42 -0600, Jan Beulich wrote:
> >
> > > > On 22.07.15 at 20:06, <toshi.kani@hp.com> wrote:
> > Add comments to the cachemode translation tables to clarify that
> > the default values are set as minimal supported mode, which are
> > necessary to handle WC and WT fallback to UC- when they are not
> > enabled.
>
> Wait - shouldn't WT fall back to UC (so to not be affected by WC
> MTRR settings)?
Well, when MTRR is set to WC, WT will become UC. So, it is not safe to
start with.
I know Luis is driving to support UC. When UC can be used for both regular
memory and IO memory, yes, it can be changed to fall back to UC. At this
point, however, UC cannot be set to regular memory. See
reserve_ram_pages_type().
Thanks,
-Toshi
next prev parent reply other threads:[~2015-07-23 14:28 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-07-22 18:06 [PATCH] x86, pat: Add comments to cachemode translation tables Toshi Kani
2015-07-23 6:42 ` Jan Beulich
2015-07-23 14:27 ` Toshi Kani [this message]
2015-07-23 14:50 ` Jan Beulich
2015-07-23 15:25 ` Toshi Kani
2015-07-23 15:36 ` Jan Beulich
2015-07-23 15:38 ` Toshi Kani
2015-08-02 10:07 ` Thomas Gleixner
2015-08-03 15:08 ` Toshi Kani
2015-08-20 19:30 ` [tip:x86/mm] x86/mm/pat: " tip-bot for Toshi Kani
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