From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751663AbbHNS2T (ORCPT ); Fri, 14 Aug 2015 14:28:19 -0400 Received: from mail-wi0-f176.google.com ([209.85.212.176]:37582 "EHLO mail-wi0-f176.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751795AbbHNS2P (ORCPT ); Fri, 14 Aug 2015 14:28:15 -0400 From: Robert Richter To: Marc Zygnier , Thomas Gleixner , Jason Cooper Cc: Tirumalesh Chalamarla , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Robert Richter Subject: [PATCH v4 0/5] irqchip, gicv3: Updates and Cavium ThunderX errata workarounds Date: Fri, 14 Aug 2015 20:28:00 +0200 Message-Id: <1439576885-15621-1-git-send-email-rric@kernel.org> X-Mailer: git-send-email 2.1.1 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Robert Richter This patch series adds gicv3 updates and workarounds for HW errata in Cavium's ThunderX GICV3. The first one is an unchanged resubmission of a patch from a gicv3 series I sent a while ago. The next patches implement the workarounds for ThunderX's gicv3. Patch #2 implements the cpu workaround for gicv3 on ThunderX. Patch #3 is a prerequisit for patch #5. Patch #4 adds generic code to parse the hw revision provided by an IIDR. This patch is used for the implementa- tion of the actual gicv3-its workaround in #5. All current review comments addressed so far with v4. v4: * simplify code to only use cpus_have_cap() in gicv3_enable_quirks() * only enable hw detection for its in its_enable_quirks() * removed gicv3_check_capabilities() * drop special cpu capability for zero v3: * use arm64 errata framework for midr check * fix mixup of errata to be dependend from midr/iidr v2: * Workaround for 23154: * implement code in a single asm() to keep instruction sequence * added comment to the code that explains the erratum * apply workaround also if running as guest, thus check MIDR * adding MIDR check Robert Richter (5): irqchip, gicv3-its: Add range check for number of allocated pages irqchip, gicv3: Workaround for Cavium ThunderX erratum 23154 irqchip, gicv3-its: Read typer register outside the loop irqchip, gicv3-its: Add HW revision detection and configuration irqchip, gicv3-its: Workaround for Cavium ThunderX errata 22375, 24313 arch/arm64/Kconfig | 11 +++++++ arch/arm64/include/asm/cpufeature.h | 3 +- arch/arm64/include/asm/cputype.h | 18 ++++++----- arch/arm64/kernel/cpu_errata.c | 9 ++++++ drivers/irqchip/irq-gic-common.c | 11 +++++++ drivers/irqchip/irq-gic-common.h | 9 ++++++ drivers/irqchip/irq-gic-v3-its.c | 62 +++++++++++++++++++++++++++++++++---- drivers/irqchip/irq-gic-v3.c | 42 ++++++++++++++++++++++++- include/linux/irqchip/arm-gic-v3.h | 1 + 9 files changed, 151 insertions(+), 15 deletions(-) -- 2.1.1