From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754872AbbHQLnR (ORCPT ); Mon, 17 Aug 2015 07:43:17 -0400 Received: from mga09.intel.com ([134.134.136.24]:58461 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751073AbbHQLnP (ORCPT ); Mon, 17 Aug 2015 07:43:15 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.15,694,1432623600"; d="scan'208";a="626934083" From: "Chen, Yu C" To: "mingo@kernel.org" CC: "linux-kernel@vger.kernel.org" , "Zhang, Rui" , "tglx@linutronix.de" , "linux-pm@vger.kernel.org" , "pavel@ucw.cz" , "x86@kernel.org" , "hpa@zytor.com" , "rjw@rjwysocki.net" , "mingo@redhat.com" Subject: Re: [PATCH] x86, suspend: Save/restore THERM_CONTROL register for suspend Thread-Topic: [PATCH] x86, suspend: Save/restore THERM_CONTROL register for suspend Thread-Index: AQHQ2MZru7x2/qnU/0+qScQ+o74RiJ4PcnCAgAAanoA= Date: Mon, 17 Aug 2015 11:43:02 +0000 Message-ID: <1439811991.15722.26.camel@localhost> References: <1439800192-3034-1-git-send-email-yu.c.chen@intel.com> <20150817101115.GA27204@gmail.com> In-Reply-To: <20150817101115.GA27204@gmail.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.160.87] Content-Type: text/plain; charset="utf-8" Content-ID: MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id t7HBhWft009817 Hi, Ingo, thanks for your review, On Mon, 2015-08-17 at 12:11 +0200, Ingo Molnar wrote: > So what your changelog fails to mention: > > - You only add this code to the 64-bit kernel. Are 32-bit kernels not affected? Yes, 32-bit kernel should also do the save/restore operation. I'll adjust them to 64/32-bit common path. > > - the MSR read is done unconditionally. Is MSR_IA32_THERM_CONTROL available > architecturally and readable (and has sensible values) on all 64-bit capable > x86 CPUs that run this code path? MSR_IA32_THERM_CONTROL is available on Intel Pentium 4, Xeon, Pentium M and later processors, so I think not all the 64/32-bit capable x86 CPUs have this register. Maybe codes like the following would be more reasonable? save: ctxt->clock_modulation_saved = !rdmsrl_safe(MSR_IA32_THERM_CONTROL, &ctxt->clock_modulation); restore: if (ctxt->clock_modulation_saved) wrmsrl(MSR_IA32_THERM_CONTROL, ctxt->clock_modulation); Thanks a lot. Best Regards, Yu {.n++%ݶw{.n+{G{ayʇڙ,jfhz_(階ݢj"mG?&~iOzv^m ?I