From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752314AbbIOR41 (ORCPT ); Tue, 15 Sep 2015 13:56:27 -0400 Received: from mail-gw3-out.broadcom.com ([216.31.210.64]:13449 "EHLO mail-gw3-out.broadcom.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751558AbbIOR40 (ORCPT ); Tue, 15 Sep 2015 13:56:26 -0400 X-IronPort-AV: E=Sophos;i="5.17,536,1437462000"; d="scan'208";a="75026907" From: Ray Jui To: Kishon Vijay Abraham I CC: Arnd Bergmann , , "JD (Jiandong) Zheng" , Arun Parameswaran , , Ray Jui Subject: [PATCH v3 1/2] dt-bindings: Add Broadcom Cygnus PCIe PHY binding Date: Tue, 15 Sep 2015 10:56:36 -0700 Message-ID: <1442339797-6830-2-git-send-email-rjui@broadcom.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1442339797-6830-1-git-send-email-rjui@broadcom.com> References: <1442339797-6830-1-git-send-email-rjui@broadcom.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add DT binding for Broadcom Cygnus PCIe PHYs Signed-off-by: Ray Jui Reviewed-by: Arun Parameswaran Reviewed-by: JD (Jiandong) Zheng Reviewed-by: Scott Branden --- .../bindings/phy/brcm,cygnus-pcie-phy.txt | 30 ++++++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/brcm,cygnus-pcie-phy.txt diff --git a/Documentation/devicetree/bindings/phy/brcm,cygnus-pcie-phy.txt b/Documentation/devicetree/bindings/phy/brcm,cygnus-pcie-phy.txt new file mode 100644 index 0000000..ba41143 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/brcm,cygnus-pcie-phy.txt @@ -0,0 +1,30 @@ +Broadcom Cygnus PCIe PHY + +Required properties: +- compatible: Must be "brcm,cygnus-pcie-phy" +- reg: base address and length of the PCIe PHY block +- #phy-cells: must be <1> +The first cell is the PHY ID: +0 - PCIe RC 0 +1 - PCIe RC 1 + +Example: + pcie_phy: phy@0301d0a0 { + compatible = "brcm,cygnus-pcie-phy"; + reg = <0x0301d0a0 0x14>; + #phy-cells = <1>; + }; + + pcie0: pcie@18012000 { + ... + ... + phys = <&pcie_phy 0>; + phy-names = "pcie-phy"; + }; + + pcie1: pcie@18013000 { + ... + ... + phys = <&pcie_phy 1>; + phy-names = "pcie-phy"; + }; -- 1.9.1