From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758125AbbIVP1h (ORCPT ); Tue, 22 Sep 2015 11:27:37 -0400 Received: from mail-by2on0081.outbound.protection.outlook.com ([207.46.100.81]:63299 "EHLO na01-by2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751621AbbIVP1d (ORCPT ); Tue, 22 Sep 2015 11:27:33 -0400 Authentication-Results: spf=fail (sender IP is 66.35.236.227) smtp.mailfrom=opensource.altera.com; ettus.com; dkim=none (message not signed) header.d=none;ettus.com; dmarc=none action=none header.from=opensource.altera.com; Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=atull@opensource.altera.com; From: To: , , , , , CC: Moritz Fischer , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Petr Cvek , , , Alan Tull Subject: [PATCH v11 1/4] usage documentation for FPGA manager core Date: Tue, 22 Sep 2015 10:21:08 -0500 Message-ID: <1442935271-10375-2-git-send-email-atull@opensource.altera.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1442935271-10375-1-git-send-email-atull@opensource.altera.com> References: <1442935271-10375-1-git-send-email-atull@opensource.altera.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [64.129.157.38] X-ClientProxiedBy: BY2PR1001CA0082.namprd10.prod.outlook.com (25.164.163.50) To BY1PR03MB1516.namprd03.prod.outlook.com (25.162.210.15) X-Microsoft-Exchange-Diagnostics-untrusted: 1;BY1PR03MB1516;2:sFfMv6n0VQsZr0eRXTF42ZqvznxrNB7g0y0IHbyoD7hUZH+31X2CAffKjmPzH/X7wDSIDxl+YZJNvaePtM1Ux45AaXWP8EDEaGe9p2oZ1pSygNcOGN8LMrGpqZibxoBFAGQ5hpvWIwiOMy/h0mqI463rB9dsdRNOTIjBfsdqIxI=;3:D0wUAd8qXSOp64cVTMF1ppawhH8flWnEIVmyg9HlANVuFJCgG77hyJVhad84TxTWmJ6sT69AUxvOiQgWTr07ClYfZRS5IyGXBfRNibAeVhG5zBqB+PiE42zS2V6TM2wC3w6KLf7NZTC1tzACSL6/Kw==;25:2hsoAyMnajw+4lqoW1sfRkIIjrv74LiYR30ur3TNihttaVghzr07hFhGtaJsTXIlHQR1OAPkOUC5fEQRf/L36vQuVm6Eas/Prz827VFHFjLiMOHIGfH24UN8aDUZmqOKEt0IKkUEs+rIf6pvLmwp4Nz7c3dDsCNSfPMTEklX8LacKKXzttFoGxLHTCYNjtE3tkT2zy8LuvJb5UqsgaXmEGHU+AHcYq3lHKHPloyX+h+XbVOCDMbqfqhYmYxlvFrNdnw4m52FaazKtHfcq8JMxA==;20:3OVDrEDjoc3a3Eaj9uy1kRjpXtS0ciYRm0HF9GqwB1W0Dtr4/pe+1U7RlUHa4TL1JzOM11qQZdD7qsZV1/Rs8VmtSmHQlKruiD6va3Lrqi2kulJFZtJQWF9PgxA4YoL7TAiRE2CwtIfGd4NNaKRVLVs0LBHpd+pOC3BZVVdS0Z8= X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BY1PR03MB1516;UriScan:;BCL:0;PCL:0;RULEID:;SRVR:SN2PR03MB047; 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Signed-off-by: Alan Tull --- v9: initial version where this patch was added v10: requested cleanups to formatting and otherwise s/fpga/FPGA/g rewrite implementation section to not reference socfpga.c by name other rewrites Moved to Documentation/fpga/ v11: s/with image/with an image/ s/on the path/in the path/ --- Documentation/fpga/fpga-mgr.txt | 171 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 171 insertions(+) create mode 100644 Documentation/fpga/fpga-mgr.txt diff --git a/Documentation/fpga/fpga-mgr.txt b/Documentation/fpga/fpga-mgr.txt new file mode 100644 index 0000000..ce3e84f --- /dev/null +++ b/Documentation/fpga/fpga-mgr.txt @@ -0,0 +1,171 @@ +FPGA Manager Core + +Alan Tull 2015 + +Overview +======== + +The FPGA manager core exports a set of functions for programming an FPGA with +an image. The API is manufacturer agnostic. All manufacturer specifics are +hidden away in a low level driver which registers a set of ops with the core. +The FPGA image data itself is very manufacturer specific, but for our purposes +it's just binary data. The FPGA manager core won't parse it. + + +API Functions: +============== + +To program the FPGA from a file or from a buffer: +------------------------------------------------- + + int fpga_mgr_buf_load(struct fpga_manager *mgr, u32 flags, + const char *buf, size_t count); + +Load the FPGA from an image which exists as a buffer in memory. + + int fpga_mgr_firmware_load(struct fpga_manager *mgr, u32 flags, + const char *image_name); + +Load the FPGA from an image which exists as a file. The image file must be on +the firmware search path (see the firmware class documentation). + +For both these functions, flags == 0 for normal full reconfiguration or +FPGA_MGR_PARTIAL_RECONFIG for partial reconfiguration. If successful, the FPGA +ends up in operating mode. Return 0 on success or a negative error code. + + +To get/put a reference to a FPGA manager: +----------------------------------------- + + struct fpga_manager *of_fpga_mgr_get(struct device_node *node); + + void fpga_mgr_put(struct fpga_manager *mgr); + +Given a DT node, get an exclusive reference to a FPGA manager or release +the reference. + + +To register or unregister the low level FPGA-specific driver: +------------------------------------------------------------- + + int fpga_mgr_register(struct device *dev, const char *name, + const struct fpga_manager_ops *mops, + void *priv); + + void fpga_mgr_unregister(struct device *dev); + +Use of these two functions is described below in "How To Support a new FPGA +device." + + +How to write an image buffer to a supported FPGA +================================================ +/* Include to get the API */ +#include + +/* device node that specifies the FPGA manager to use */ +struct device_node *mgr_node = ... + +/* FPGA image is in this buffer. count is size of the buffer. */ +char *buf = ... +int count = ... + +/* flags indicates whether to do full or partial reconfiguration */ +int flags = 0; + +int ret; + +/* Get exclusive control of FPGA manager */ +struct fpga_manager *mgr = of_fpga_mgr_get(mgr_node); + +/* Load the buffer to the FPGA */ +ret = fpga_mgr_buf_load(mgr, flags, buf, count); + +/* Release the FPGA manager */ +fpga_mgr_put(mgr); + + +How to write an image file to a supported FPGA +============================================== +/* Include to get the API */ +#include + +/* device node that specifies the FPGA manager to use */ +struct device_node *mgr_node = ... + +/* FPGA image is in this file which is in the firmware search path */ +const char *path = "fpga-image-9.rbf" + +/* flags indicates whether to do full or partial reconfiguration */ +int flags = 0; + +int ret; + +/* Get exclusive control of FPGA manager */ +struct fpga_manager *mgr = of_fpga_mgr_get(mgr_node); + +/* Get the firmware image (path) and load it to the FPGA */ +ret = fpga_mgr_firmware_load(mgr, flags, path); + +/* Release the FPGA manager */ +fpga_mgr_put(mgr); + + +How to support a new FPGA device +================================ +To add another FPGA manager, write a driver that implements a set of ops. The +probe function calls fpga_mgr_register(), such as: + +static const struct fpga_manager_ops socfpga_fpga_ops = { + .write_init = socfpga_fpga_ops_configure_init, + .write = socfpga_fpga_ops_configure_write, + .write_complete = socfpga_fpga_ops_configure_complete, + .state = socfpga_fpga_ops_state, +}; + +static int socfpga_fpga_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct socfpga_fpga_priv *priv; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + /* ... do ioremaps, get interrupts, etc. and save + them in priv... */ + + return fpga_mgr_register(dev, "Altera SOCFPGA FPGA Manager", + &socfpga_fpga_ops, priv); +} + +static int socfpga_fpga_remove(struct platform_device *pdev) +{ + fpga_mgr_unregister(&pdev->dev); + + return 0; +} + + +The ops will implement whatever device specific register writes are needed to +do the programming sequence for this particular FPGA. These ops return 0 for +success or negative error codes otherwise. + +The programming sequence is: + 1. .write_init + 2. .write (may be called once or multiple times) + 3. .write_complete + +The .write_init function will prepare the FPGA to receive the image data. + +The .write function writes a buffer to the FPGA. The buffer may be contain the +whole FPGA image or may be a smaller chunk of an FPGA image. In the latter +case, this function is called multiple times for successive chunks. + +The .write_complete function is called after all the image has been written +to put the FPGA into operating mode. + +The ops include a .state function which will read the hardware FPGA manager and +return a code of type enum fpga_mgr_states. It doesn't result in a change in +hardware state. -- 1.7.9.5