From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933732AbbIVPzw (ORCPT ); Tue, 22 Sep 2015 11:55:52 -0400 Received: from mga03.intel.com ([134.134.136.65]:37833 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933521AbbIVPyS (ORCPT ); Tue, 22 Sep 2015 11:54:18 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.17,573,1437462000"; d="scan'208";a="566326391" From: Andy Shevchenko To: Stephen Boyd , linux-kernel@vger.kernel.org, heikki.krogerus@linux.intel.com, linux-clk@vger.kernel.org Cc: Andy Shevchenko Subject: [PATCH v6 4/5] clk: fractional-divider: switch to rational best approximation Date: Tue, 22 Sep 2015 18:54:11 +0300 Message-Id: <1442937252-50281-5-git-send-email-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.5.1 In-Reply-To: <1442937252-50281-1-git-send-email-andriy.shevchenko@linux.intel.com> References: <1442937252-50281-1-git-send-email-andriy.shevchenko@linux.intel.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch converts the code to use rational best approximation algorithm which is much more precise. Suggested-by: Stephen Boyd Reviewed-by: Heikki Krogerus Signed-off-by: Andy Shevchenko --- drivers/clk/Kconfig | 1 + drivers/clk/clk-fractional-divider.c | 41 +++++++++++++++++++++++------------- 2 files changed, 27 insertions(+), 15 deletions(-) diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 42f7120..bd9f312 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -14,6 +14,7 @@ config COMMON_CLK select HAVE_CLK_PREPARE select CLKDEV_LOOKUP select SRCU + select RATIONAL ---help--- The common clock framework is a single definition of struct clk, useful across many platforms, as well as an diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c index 0282c76..5c4955e 100644 --- a/drivers/clk/clk-fractional-divider.c +++ b/drivers/clk/clk-fractional-divider.c @@ -7,13 +7,14 @@ * * Adjustable fractional divider clock implementation. * Output rate = (m / n) * parent_rate. + * Uses rational best approximation algorithm. */ #include #include #include #include -#include +#include #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw) @@ -22,7 +23,8 @@ static unsigned long clk_fd_recalc_rate(struct clk_hw *hw, { struct clk_fractional_divider *fd = to_clk_fd(hw); unsigned long flags = 0; - u32 val, m, n; + unsigned long m, n; + u32 val; u64 ret; if (fd->lock) @@ -53,20 +55,30 @@ static long clk_fd_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { struct clk_fractional_divider *fd = to_clk_fd(hw); - unsigned maxn = (fd->nmask >> fd->nshift) + 1; - unsigned div; + unsigned long scale; + unsigned long m, n; + u64 ret; if (!rate || rate >= *parent_rate) return *parent_rate; - div = gcd(*parent_rate, rate); + /* + * Get rate closer to *parent_rate to guarantee there is no overflow + * for m and n. In the result it will be the nearest rate left shifted + * by (scale - fd->nwidth) bits. + */ + scale = fls_long(*parent_rate / rate - 1); + if (scale > fd->nwidth) + rate <<= scale - fd->nwidth; - while ((*parent_rate / div) > maxn) { - div <<= 1; - rate <<= 1; - } + rational_best_approximation(rate, *parent_rate, + GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0), + &m, &n); - return rate; + ret = (u64)*parent_rate * m; + do_div(ret, n); + + return ret; } static int clk_fd_set_rate(struct clk_hw *hw, unsigned long rate, @@ -74,13 +86,12 @@ static int clk_fd_set_rate(struct clk_hw *hw, unsigned long rate, { struct clk_fractional_divider *fd = to_clk_fd(hw); unsigned long flags = 0; - unsigned long div; - unsigned n, m; + unsigned long m, n; u32 val; - div = gcd(parent_rate, rate); - m = rate / div; - n = parent_rate / div; + rational_best_approximation(rate, parent_rate, + GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0), + &m, &n); if (fd->lock) spin_lock_irqsave(fd->lock, flags); -- 2.5.1