From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751798AbbJCCZ4 (ORCPT ); Fri, 2 Oct 2015 22:25:56 -0400 Received: from e39.co.us.ibm.com ([32.97.110.160]:33407 "EHLO e39.co.us.ibm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751503AbbJCCZy (ORCPT ); Fri, 2 Oct 2015 22:25:54 -0400 X-IBM-Helo: d03dlp01.boulder.ibm.com X-IBM-MailFrom: bergner@vnet.ibm.com X-IBM-RcptTo: linux-kernel@vger.kernel.org Subject: Re: Missing operand for tlbie instruction on Power7 From: Peter Bergner To: Segher Boessenkool Cc: Denis Kirjanov , "linuxppc-dev@lists.ozlabs.org" , Laura Abbott , Paul Mackerras , Linux Kernel Mailing List In-Reply-To: <20151002220051.GA26712@gate.crashing.org> References: <560EA623.1040300@redhat.com> <1443816930.13186.214.camel@otta> <20151002220051.GA26712@gate.crashing.org> Content-Type: text/plain; charset="UTF-8" Date: Fri, 02 Oct 2015 21:24:46 -0500 Message-ID: <1443839086.13186.219.camel@otta> Mime-Version: 1.0 X-Mailer: Evolution 2.32.3 (2.32.3-30.el6) Content-Transfer-Encoding: 7bit X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 15100302-0033-0000-0000-00000630E8D3 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 2015-10-02 at 17:00 -0500, Segher Boessenkool wrote: > On Sat, Oct 03, 2015 at 12:37:35AM +0300, Denis Kirjanov wrote: > > >> -0: tlbie r4; \ > > >> +0: tlbie r4, 0; \ > > > > > > This isn't correct. With POWER7 and later (which this compile > > > is, since it's on LE), the tlbie instruction takes two register > > > operands: > > > > > > tlbie RB, RS > > > > > > The tlbie instruction on pre POWER7 cpus had one required register > > > operand (RB) and an optional second L operand, where if you omitted > > > it, it was the same as using "0": > > > > > > tlbie RB, L > > > > > > This is a POWER7 and later build, so your change which adds the "0" > > > above is really adding r0 for RS. The new tlbie instruction doesn't > > > treat r0 specially, so you'll be using whatever random bits which > > > happen to be in r0 which I don't think that is what you want. > > > > Ok, than we can just zero out r5 for example and use it in tlbie as RS, > > right? > > That won't assemble _unless_ your assembler is in POWER7 mode. It also > won't do the right thing at run time on older machines. Correct, getting this to work on both pre-power7 and power7 and later is tricky. One really horrible hack would be to do: li r0,0 tlbie r4,0 On pre-power7, the "0" will be taken as a zero L operand and on power7 and later, it'll be r0, but with a zero value we loaded in the insn before. I know, really ugly. :-) Peter