From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752198AbbJEMKi (ORCPT ); Mon, 5 Oct 2015 08:10:38 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:15468 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752096AbbJEMKe (ORCPT ); Mon, 5 Oct 2015 08:10:34 -0400 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Mon, 05 Oct 2015 05:03:18 -0700 From: Jon Hunter To: Laxman Dewangan , Vinod Koul , Stephen Warren , Thierry Reding , Alexandre Courbot , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Arnd Bergmann CC: , , , Jon Hunter Subject: [PATCH V2 1/2] Documentation: DT: Add binding documentation for NVIDIA ADMA Date: Mon, 5 Oct 2015 13:10:06 +0100 Message-ID: <1444047007-30494-2-git-send-email-jonathanh@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1444047007-30494-1-git-send-email-jonathanh@nvidia.com> References: <1444047007-30494-1-git-send-email-jonathanh@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add device-tree binding documentation for the Tegra210 Audio DMA controller. Signed-off-by: Jon Hunter --- .../devicetree/bindings/dma/tegra210-adma.txt | 63 ++++++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/tegra210-adma.txt diff --git a/Documentation/devicetree/bindings/dma/tegra210-adma.txt b/Documentation/devicetree/bindings/dma/tegra210-adma.txt new file mode 100644 index 000000000000..df0e46868a63 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/tegra210-adma.txt @@ -0,0 +1,63 @@ +* NVIDIA Tegra Audio DMA (ADMA) controller + +Required properties: +- compatible: Must be "nvidia,tegra210-adma". +- reg: Should contain DMA registers location and length. This should be + a single entry that includes all of the per-channel registers in one + contiguous bank. +- interrupt-parent: Phandle to the interrupt parent controller. +- interrupts: Should contain all of the per-channel DMA interrupts in + ascending order with respect to the DMA channel index. +- clocks: Must contain one entry for the ADMA module clock, "adma_ape". +- clock-names: Must contain the entry "adma_ape". +- dma-channels: Must be 22. Defines the number of DMA channels supported + by the DMA controller. +- dma-rx-requests: Must be 10. Defines the number of receive request + signals supported by the DMA controller. +- dma-tx-requests: Must be 10. Defines the number of transmit request + signals supported by the DMA controller. +- #dma-cells : Must be <2>. The first cell denotes the transmit or + receive request number and should be between 1 and the maximum number + of requests supported (see properties "dma-rx-requests" and + "dma-tx-requests"). This value corresponds to the RX/TX_REQUEST_SELECT + fields in the ADMA_CHn_CTRL register. The second cell denotes whether + the channel is a receive or transmit channel and must be either 2 for + a receive channel and 4 for a transmit channel. These values correspond + to the TRANSFER_DIRECTION field of the ADMA_CHn_CTRL register. + + +Example: + +adma: adma@702e2000 { + compatible = "nvidia,tegra210-adma"; + reg = <0x0 0x702e2000 0x0 0x2000>; + interrupt-parent = <&tegra_agic>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&tegra_car TEGRA210_CLK_ADMA_APE>; + clock-names = "adma_ape"; + dma-channels = <22>; + dma-rx-requests = <10>; + dma-tx-requests = <10>; + #dma-cells = <2>; +}; -- 2.1.4