[PATCH v5 0/8] clk: replace div_mask() by GENMASK()

[PATCH v5 0/8] clk: replace div_mask() by GENMASK()

[Andy Shevchenko]

This series replaces div_mask() and similar macros in many clock providers by
GENMASK() generic helper.

Changelog v5:
 - amend patch for softpga by covering all cases
 - extend patchset to hisilicon and bcm clk implementation
 - rebase on top of clk-next

Changelog v4:
 - use GENMASK() instead of div_mask() by Stephen Boyd's comment

Changelog v3:
 - fix clk_div_mask() prototype: seems tired like on Friday evening!

Changelog v2:
 - fix patches 5,6,7 where parameter of the macro was d instead of d->width

Andy Shevchenko (8):
  clk: divider: switch to GENMASK()
  clk: mmp: switch to GENMASK()
  clk: socfpga: switch to GENMASK()
  clk: ti: divider: switch to GENMASK()
  clk: tegra: switch to GENMASK()
  clk: hisilicon: switch to GENMASK()
  clk: bcm: switch to GENMASK()
  ARM: imx: switch to GENMASK()

 drivers/clk/bcm/clk-iproc-asiu.c          | 22 ++++++++--------------
 drivers/clk/bcm/clk-iproc-pll.c           | 31 ++++++++++++++-----------------
 drivers/clk/bcm/clk-iproc.h               |  1 -
 drivers/clk/bcm/clk-kona-setup.c          |  2 +-
 drivers/clk/bcm/clk-kona.c                | 12 +++---------
 drivers/clk/clk-divider.c                 | 18 ++++++++----------
 drivers/clk/hisilicon/clkdivider-hi6220.c |  8 +++-----
 drivers/clk/imx/clk-fixup-div.c           |  7 +++----
 drivers/clk/mmp/clk-mix.c                 |  2 +-
 drivers/clk/mmp/clk.h                     |  2 +-
 drivers/clk/socfpga/clk-gate-a10.c        |  2 +-
 drivers/clk/socfpga/clk-gate.c            |  2 +-
 drivers/clk/socfpga/clk-periph-a10.c      |  2 +-
 drivers/clk/socfpga/clk-periph.c          |  2 +-
 drivers/clk/socfpga/clk.h                 |  1 -
 drivers/clk/tegra/clk-divider.c           |  7 +++----
 drivers/clk/tegra/clk-pll.c               | 13 ++++++-------
 drivers/clk/tegra/clk-super.c             |  2 +-
 drivers/clk/ti/divider.c                  | 18 ++++++++----------
 19 files changed, 64 insertions(+), 90 deletions(-)

-- 
2.1.4

[PATCH v5 1/8] clk: divider: switch to GENMASK()

[Andy Shevchenko]

Convert the code to use GENMASK() helper instead of div_mask() macro.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 drivers/clk/clk-divider.c | 18 ++++++++----------
 1 file changed, 8 insertions(+), 10 deletions(-)

diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 706b578..3bde790 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -30,8 +30,6 @@
 
 #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
 
-#define div_mask(width)	((1 << (width)) - 1)
-
 static unsigned int _get_table_maxdiv(const struct clk_div_table *table)
 {
 	unsigned int maxdiv = 0;
@@ -58,12 +56,12 @@ static unsigned int _get_maxdiv(const struct clk_div_table *table, u8 width,
 				unsigned long flags)
 {
 	if (flags & CLK_DIVIDER_ONE_BASED)
-		return div_mask(width);
+		return GENMASK(width - 1, 0);
 	if (flags & CLK_DIVIDER_POWER_OF_TWO)
-		return 1 << div_mask(width);
+		return GENMASK(width - 1, 0);
 	if (table)
 		return _get_table_maxdiv(table);
-	return div_mask(width) + 1;
+	return BIT(width);
 }
 
 static unsigned int _get_table_div(const struct clk_div_table *table,
@@ -138,7 +136,7 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
 	unsigned int val;
 
 	val = clk_readl(divider->reg) >> divider->shift;
-	val &= div_mask(divider->width);
+	val &= GENMASK(divider->width - 1, 0);
 
 	return divider_recalc_rate(hw, parent_rate, val, divider->table,
 				   divider->flags);
@@ -350,7 +348,7 @@ static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
 	/* if read only, just return current value */
 	if (divider->flags & CLK_DIVIDER_READ_ONLY) {
 		bestdiv = readl(divider->reg) >> divider->shift;
-		bestdiv &= div_mask(divider->width);
+		bestdiv &= GENMASK(divider->width - 1, 0);
 		bestdiv = _get_div(divider->table, bestdiv, divider->flags);
 		return DIV_ROUND_UP(*prate, bestdiv);
 	}
@@ -372,7 +370,7 @@ int divider_get_val(unsigned long rate, unsigned long parent_rate,
 
 	value = _get_val(table, div, flags);
 
-	return min_t(unsigned int, value, div_mask(width));
+	return min_t(unsigned int, value, GENMASK(width - 1, 0));
 }
 EXPORT_SYMBOL_GPL(divider_get_val);
 
@@ -391,10 +389,10 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
 		spin_lock_irqsave(divider->lock, flags);
 
 	if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
-		val = div_mask(divider->width) << (divider->shift + 16);
+		val = GENMASK(divider->width - 1, 0) << (divider->shift + 16);
 	} else {
 		val = clk_readl(divider->reg);
-		val &= ~(div_mask(divider->width) << divider->shift);
+		val &= ~(GENMASK(divider->width - 1, 0) << divider->shift);
 	}
 	val |= value << divider->shift;
 	clk_writel(val, divider->reg);
-- 
2.1.4

[PATCH v5 2/8] clk: mmp: switch to GENMASK()

[Andy Shevchenko]

Convert the code to use GENMASK() helper instead of custom approach.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 drivers/clk/mmp/clk-mix.c | 2 +-
 drivers/clk/mmp/clk.h     | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/mmp/clk-mix.c b/drivers/clk/mmp/clk-mix.c
index 7a37432..1ff85d7c 100644
--- a/drivers/clk/mmp/clk-mix.c
+++ b/drivers/clk/mmp/clk-mix.c
@@ -26,7 +26,7 @@
 
 static unsigned int _get_maxdiv(struct mmp_clk_mix *mix)
 {
-	unsigned int div_mask = (1 << mix->reg_info.width_div) - 1;
+	unsigned int div_mask = GENMASK(mix->reg_info.width_div - 1, 0);
 	unsigned int maxdiv = 0;
 	struct clk_div_table *clkt;
 
diff --git a/drivers/clk/mmp/clk.h b/drivers/clk/mmp/clk.h
index adf9b71..f5fdb0e 100644
--- a/drivers/clk/mmp/clk.h
+++ b/drivers/clk/mmp/clk.h
@@ -39,7 +39,7 @@ extern struct clk *mmp_clk_register_factor(const char *name,
 
 /* Clock type "mix" */
 #define MMP_CLK_BITS_MASK(width, shift)			\
-		(((1 << (width)) - 1) << (shift))
+		(GENMASK((width) - 1, 0) << (shift))
 #define MMP_CLK_BITS_GET_VAL(data, width, shift)	\
 		((data & MMP_CLK_BITS_MASK(width, shift)) >> (shift))
 #define MMP_CLK_BITS_SET_VAL(val, width, shift)		\
-- 
2.1.4

[PATCH v5 3/8] clk: socfpga: switch to GENMASK()

[Andy Shevchenko]

Convert the code to use GENMASK() helper instead of div_mask() macro.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 drivers/clk/socfpga/clk-gate-a10.c   | 2 +-
 drivers/clk/socfpga/clk-gate.c       | 2 +-
 drivers/clk/socfpga/clk-periph-a10.c | 2 +-
 drivers/clk/socfpga/clk-periph.c     | 2 +-
 drivers/clk/socfpga/clk.h            | 1 -
 5 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/socfpga/clk-gate-a10.c b/drivers/clk/socfpga/clk-gate-a10.c
index 83c6780..8d4052a2 100644
--- a/drivers/clk/socfpga/clk-gate-a10.c
+++ b/drivers/clk/socfpga/clk-gate-a10.c
@@ -38,7 +38,7 @@ static unsigned long socfpga_gate_clk_recalc_rate(struct clk_hw *hwclk,
 		div = socfpgaclk->fixed_div;
 	else if (socfpgaclk->div_reg) {
 		val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
-		val &= div_mask(socfpgaclk->width);
+		val &= GENMASK(socfpgaclk->width - 1, 0);
 		div = (1 << val);
 	}
 
diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c
index 82449cd..dcae97c 100644
--- a/drivers/clk/socfpga/clk-gate.c
+++ b/drivers/clk/socfpga/clk-gate.c
@@ -106,7 +106,7 @@ static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
 		div = socfpgaclk->fixed_div;
 	else if (socfpgaclk->div_reg) {
 		val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
-		val &= div_mask(socfpgaclk->width);
+		val &= GENMASK(socfpgaclk->width - 1, 0);
 		/* Check for GPIO_DB_CLK by its offset */
 		if ((int) socfpgaclk->div_reg & SOCFPGA_GPIO_DB_CLK_OFFSET)
 			div = val + 1;
diff --git a/drivers/clk/socfpga/clk-periph-a10.c b/drivers/clk/socfpga/clk-periph-a10.c
index 9d0181b..4c200e5 100644
--- a/drivers/clk/socfpga/clk-periph-a10.c
+++ b/drivers/clk/socfpga/clk-periph-a10.c
@@ -37,7 +37,7 @@ static unsigned long clk_periclk_recalc_rate(struct clk_hw *hwclk,
 		div = socfpgaclk->fixed_div;
 	} else if (socfpgaclk->div_reg) {
 		div = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
-		div &= div_mask(socfpgaclk->width);
+		div &= GENMASK(socfpgaclk->width - 1, 0);
 		div += 1;
 	} else {
 		div = ((readl(socfpgaclk->hw.reg) & 0x7ff) + 1);
diff --git a/drivers/clk/socfpga/clk-periph.c b/drivers/clk/socfpga/clk-periph.c
index 83aeaa2..8b5ecae 100644
--- a/drivers/clk/socfpga/clk-periph.c
+++ b/drivers/clk/socfpga/clk-periph.c
@@ -36,7 +36,7 @@ static unsigned long clk_periclk_recalc_rate(struct clk_hw *hwclk,
 	} else {
 		if (socfpgaclk->div_reg) {
 			val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
-			val &= div_mask(socfpgaclk->width);
+			val &= GENMASK(socfpgaclk->width - 1, 0);
 			parent_rate /= (val + 1);
 		}
 		div = ((readl(socfpgaclk->hw.reg) & 0x1ff) + 1);
diff --git a/drivers/clk/socfpga/clk.h b/drivers/clk/socfpga/clk.h
index 603973a..ddbd0fa 100644
--- a/drivers/clk/socfpga/clk.h
+++ b/drivers/clk/socfpga/clk.h
@@ -27,7 +27,6 @@
 #define CLKMGR_PERPLL_SRC	0xAC
 
 #define SOCFPGA_MAX_PARENTS		5
-#define div_mask(width) ((1 << (width)) - 1)
 
 #define streq(a, b) (strcmp((a), (b)) == 0)
 #define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
-- 
2.1.4

[PATCH v5 4/8] clk: ti: divider: switch to GENMASK()

[Andy Shevchenko]

Convert the code to use GENMASK() helper instead of div_mask() macro.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 drivers/clk/ti/divider.c | 18 ++++++++----------
 1 file changed, 8 insertions(+), 10 deletions(-)

diff --git a/drivers/clk/ti/divider.c b/drivers/clk/ti/divider.c
index ff5f117..dfe485e 100644
--- a/drivers/clk/ti/divider.c
+++ b/drivers/clk/ti/divider.c
@@ -28,8 +28,6 @@
 
 #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
 
-#define div_mask(d)	((1 << ((d)->width)) - 1)
-
 static unsigned int _get_table_maxdiv(const struct clk_div_table *table)
 {
 	unsigned int maxdiv = 0;
@@ -44,12 +42,12 @@ static unsigned int _get_table_maxdiv(const struct clk_div_table *table)
 static unsigned int _get_maxdiv(struct clk_divider *divider)
 {
 	if (divider->flags & CLK_DIVIDER_ONE_BASED)
-		return div_mask(divider);
+		return GENMASK(divider->width - 1, 0);
 	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
-		return 1 << div_mask(divider);
+		return 1 << GENMASK(divider->width - 1, 0);
 	if (divider->table)
 		return _get_table_maxdiv(divider->table);
-	return div_mask(divider) + 1;
+	return BIT(divider->width);
 }
 
 static unsigned int _get_table_div(const struct clk_div_table *table,
@@ -103,7 +101,7 @@ static unsigned long ti_clk_divider_recalc_rate(struct clk_hw *hw,
 	unsigned int div, val;
 
 	val = ti_clk_ll_ops->clk_readl(divider->reg) >> divider->shift;
-	val &= div_mask(divider);
+	val &= GENMASK(divider->width - 1, 0);
 
 	div = _get_div(divider, val);
 	if (!div) {
@@ -225,17 +223,17 @@ static int ti_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
 	div = DIV_ROUND_UP(parent_rate, rate);
 	value = _get_val(divider, div);
 
-	if (value > div_mask(divider))
-		value = div_mask(divider);
+	if (value > GENMASK(divider->width - 1, 0))
+		value = GENMASK(divider->width - 1, 0);
 
 	if (divider->lock)
 		spin_lock_irqsave(divider->lock, flags);
 
 	if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
-		val = div_mask(divider) << (divider->shift + 16);
+		val = GENMASK(divider->width - 1, 0) << (divider->shift + 16);
 	} else {
 		val = ti_clk_ll_ops->clk_readl(divider->reg);
-		val &= ~(div_mask(divider) << divider->shift);
+		val &= ~(GENMASK(divider->width - 1, 0) << divider->shift);
 	}
 	val |= value << divider->shift;
 	ti_clk_ll_ops->clk_writel(val, divider->reg);
-- 
2.1.4

[PATCH v5 5/8] clk: tegra: switch to GENMASK()

[Andy Shevchenko]

Convert the code to use GENMASK() helper instead of custom approach.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 drivers/clk/tegra/clk-divider.c |  7 +++----
 drivers/clk/tegra/clk-pll.c     | 13 ++++++-------
 drivers/clk/tegra/clk-super.c   |  2 +-
 3 files changed, 10 insertions(+), 12 deletions(-)

diff --git a/drivers/clk/tegra/clk-divider.c b/drivers/clk/tegra/clk-divider.c
index 59a5714..bf7f667 100644
--- a/drivers/clk/tegra/clk-divider.c
+++ b/drivers/clk/tegra/clk-divider.c
@@ -24,9 +24,8 @@
 #include "clk.h"
 
 #define pll_out_override(p) (BIT((p->shift - 6)))
-#define div_mask(d) ((1 << (d->width)) - 1)
 #define get_mul(d) (1 << d->frac_width)
-#define get_max_div(d) div_mask(d)
+#define get_max_div(d) GENMASK(d->width - 1, 0)
 
 #define PERIPH_CLK_UART_DIV_ENB BIT(24)
 
@@ -73,7 +72,7 @@ static unsigned long clk_frac_div_recalc_rate(struct clk_hw *hw,
 	u64 rate = parent_rate;
 
 	reg = readl_relaxed(divider->reg) >> divider->shift;
-	div = reg & div_mask(divider);
+	div = reg & GENMASK(divider->width - 1, 0);
 
 	mul = get_mul(divider);
 	div += mul;
@@ -120,7 +119,7 @@ static int clk_frac_div_set_rate(struct clk_hw *hw, unsigned long rate,
 		spin_lock_irqsave(divider->lock, flags);
 
 	val = readl_relaxed(divider->reg);
-	val &= ~(div_mask(divider) << divider->shift);
+	val &= ~(GENMASK(divider->width - 1, 0) << divider->shift);
 	val |= div << divider->shift;
 
 	if (divider->flags & TEGRA_DIVIDER_UART) {
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 05c6d08..c8488b5 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -39,13 +39,13 @@
 #define PLL_MISC_DCCON_SHIFT 20
 #define PLL_MISC_CPCON_SHIFT 8
 #define PLL_MISC_CPCON_WIDTH 4
-#define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1)
+#define PLL_MISC_CPCON_MASK GENMASK(PLL_MISC_CPCON_WIDTH - 1, 0)
 #define PLL_MISC_LFCON_SHIFT 4
 #define PLL_MISC_LFCON_WIDTH 4
-#define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1)
+#define PLL_MISC_LFCON_MASK GENMASK(PLL_MISC_LFCON_WIDTH - 1, 0)
 #define PLL_MISC_VCOCON_SHIFT 0
 #define PLL_MISC_VCOCON_WIDTH 4
-#define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1)
+#define PLL_MISC_VCOCON_MASK GENMASK(PLL_MISC_VCOCON_WIDTH - 1, 0)
 
 #define OUT_OF_TABLE_CPCON 8
 
@@ -193,11 +193,10 @@
 #define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p)
 #define pll_override_writel(val, offset, p) writel(val, p->pmc + offset)
 
-#define mask(w) ((1 << (w)) - 1)
-#define divm_mask(p) mask(p->params->div_nmp->divm_width)
-#define divn_mask(p) mask(p->params->div_nmp->divn_width)
+#define divm_mask(p) GENMASK(p->params->div_nmp->divm_width - 1, 0)
+#define divn_mask(p) GENMASK(p->params->div_nmp->divn_width - 1, 0)
 #define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\
-		      mask(p->params->div_nmp->divp_width))
+		      GENMASK(p->params->div_nmp->divp_width - 1, 0))
 
 #define divm_shift(p) (p)->params->div_nmp->divm_shift
 #define divn_shift(p) (p)->params->div_nmp->divn_shift
diff --git a/drivers/clk/tegra/clk-super.c b/drivers/clk/tegra/clk-super.c
index 2fd924d..e31e741 100644
--- a/drivers/clk/tegra/clk-super.c
+++ b/drivers/clk/tegra/clk-super.c
@@ -38,7 +38,7 @@
 
 #define super_state(s) (BIT(s) << SUPER_STATE_SHIFT)
 #define super_state_to_src_shift(m, s) ((m->width * s))
-#define super_state_to_src_mask(m) (((1 << m->width) - 1))
+#define super_state_to_src_mask(m) GENMASK(m->width - 1, 0)
 
 static u8 clk_super_get_parent(struct clk_hw *hw)
 {
-- 
2.1.4

[PATCH v5 6/8] clk: hisilicon: switch to GENMASK()

[Andy Shevchenko]

Convert the code to use GENMASK() helper instead of div_mask() macro.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 drivers/clk/hisilicon/clkdivider-hi6220.c | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/hisilicon/clkdivider-hi6220.c b/drivers/clk/hisilicon/clkdivider-hi6220.c
index 113eee8..65ab03f 100644
--- a/drivers/clk/hisilicon/clkdivider-hi6220.c
+++ b/drivers/clk/hisilicon/clkdivider-hi6220.c
@@ -18,8 +18,6 @@
 #include <linux/err.h>
 #include <linux/spinlock.h>
 
-#define div_mask(width)	((1 << (width)) - 1)
-
 /**
  * struct hi6220_clk_divider - divider clock for hi6220
  *
@@ -51,7 +49,7 @@ static unsigned long hi6220_clkdiv_recalc_rate(struct clk_hw *hw,
 	struct hi6220_clk_divider *dclk = to_hi6220_clk_divider(hw);
 
 	val = readl_relaxed(dclk->reg) >> dclk->shift;
-	val &= div_mask(dclk->width);
+	val &= GENMASK(dclk->width - 1, 0);
 
 	return divider_recalc_rate(hw, parent_rate, val, dclk->table,
 				   CLK_DIVIDER_ROUND_CLOSEST);
@@ -81,7 +79,7 @@ static int hi6220_clkdiv_set_rate(struct clk_hw *hw, unsigned long rate,
 		spin_lock_irqsave(dclk->lock, flags);
 
 	data = readl_relaxed(dclk->reg);
-	data &= ~(div_mask(dclk->width) << dclk->shift);
+	data &= ~(GENMASK(dclk->width - 1, 0) << dclk->shift);
 	data |= value << dclk->shift;
 	data |= dclk->mask;
 
@@ -116,7 +114,7 @@ struct clk *hi6220_register_clkdiv(struct device *dev, const char *name,
 		return ERR_PTR(-ENOMEM);
 
 	/* Init the divider table */
-	max_div = div_mask(width) + 1;
+	max_div = BIT(width);
 	min_div = 1;
 
 	table = kcalloc(max_div + 1, sizeof(*table), GFP_KERNEL);
-- 
2.1.4

[PATCH v5 7/8] clk: bcm: switch to GENMASK()

[Andy Shevchenko]

Convert the code to use GENMASK() helper instead of custom approach.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 drivers/clk/bcm/clk-iproc-asiu.c | 22 ++++++++--------------
 drivers/clk/bcm/clk-iproc-pll.c  | 31 ++++++++++++++-----------------
 drivers/clk/bcm/clk-iproc.h      |  1 -
 drivers/clk/bcm/clk-kona-setup.c |  2 +-
 drivers/clk/bcm/clk-kona.c       | 12 +++---------
 5 files changed, 26 insertions(+), 42 deletions(-)

diff --git a/drivers/clk/bcm/clk-iproc-asiu.c b/drivers/clk/bcm/clk-iproc-asiu.c
index f630e1b..0db9c2b 100644
--- a/drivers/clk/bcm/clk-iproc-asiu.c
+++ b/drivers/clk/bcm/clk-iproc-asiu.c
@@ -96,9 +96,11 @@ static unsigned long iproc_asiu_clk_recalc_rate(struct clk_hw *hw,
 	}
 
 	/* clock rate = parent rate / (high_div + 1) + (low_div + 1) */
-	div_h = (val >> clk->div.high_shift) & bit_mask(clk->div.high_width);
+	div_h = val >> clk->div.high_shift;
+	div_h &= GENMASK(clk->div.high_width - 1, 0);
 	div_h++;
-	div_l = (val >> clk->div.low_shift) & bit_mask(clk->div.low_width);
+	div_l = val >> clk->div.low_shift;
+	div_l &= GENMASK(clk->div.low_width - 1, 0);
 	div_l++;
 
 	clk->rate = parent_rate / (div_h + div_l);
@@ -155,20 +157,12 @@ static int iproc_asiu_clk_set_rate(struct clk_hw *hw, unsigned long rate,
 
 	val = readl(asiu->div_base + clk->div.offset);
 	val |= 1 << clk->div.en_shift;
-	if (div_h) {
-		val &= ~(bit_mask(clk->div.high_width)
-			 << clk->div.high_shift);
+	val &= ~(GENMASK(clk->div.high_width - 1, 0) << clk->div.high_shift);
+	if (div_h)
 		val |= div_h << clk->div.high_shift;
-	} else {
-		val &= ~(bit_mask(clk->div.high_width)
-			 << clk->div.high_shift);
-	}
-	if (div_l) {
-		val &= ~(bit_mask(clk->div.low_width) << clk->div.low_shift);
+	val &= ~(GENMASK(clk->div.low_width - 1, 0) << clk->div.low_shift);
+	if (div_l)
 		val |= div_l << clk->div.low_shift;
-	} else {
-		val &= ~(bit_mask(clk->div.low_width) << clk->div.low_shift);
-	}
 	writel(val, asiu->div_base + clk->div.offset);
 
 	return 0;
diff --git a/drivers/clk/bcm/clk-iproc-pll.c b/drivers/clk/bcm/clk-iproc-pll.c
index 2dda4e8..6d467ed 100644
--- a/drivers/clk/bcm/clk-iproc-pll.c
+++ b/drivers/clk/bcm/clk-iproc-pll.c
@@ -154,7 +154,7 @@ static void __pll_disable(struct iproc_pll *pll)
 	writel(val, pll->pwr_base + ctrl->aon.offset);
 
 	/* power down the core */
-	val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift);
+	val &= ~(GENMASK(ctrl->aon.pwr_width - 1, 0) << ctrl->aon.pwr_shift);
 	writel(val, pll->pwr_base + ctrl->aon.offset);
 }
 
@@ -165,7 +165,7 @@ static int __pll_enable(struct iproc_pll *pll)
 
 	/* power up the PLL and make sure it's not latched */
 	val = readl(pll->pwr_base + ctrl->aon.offset);
-	val |= bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift;
+	val |= GENMASK(ctrl->aon.pwr_width - 1, 0) << ctrl->aon.pwr_shift;
 	val &= ~(1 << ctrl->aon.iso_shift);
 	writel(val, pll->pwr_base + ctrl->aon.offset);
 
@@ -200,9 +200,9 @@ static void __pll_bring_out_reset(struct iproc_pll *pll, unsigned int kp,
 	const struct iproc_pll_reset_ctrl *reset = &ctrl->reset;
 
 	val = readl(pll->pll_base + reset->offset);
-	val &= ~(bit_mask(reset->ki_width) << reset->ki_shift |
-		 bit_mask(reset->kp_width) << reset->kp_shift |
-		 bit_mask(reset->ka_width) << reset->ka_shift);
+	val &= ~(GENMASK(reset->ki_width - 1, 0) << reset->ki_shift |
+		 GENMASK(reset->kp_width - 1, 0) << reset->kp_shift |
+		 GENMASK(reset->ka_width - 1, 0) << reset->ka_shift);
 	val |=  ki << reset->ki_shift | kp << reset->kp_shift |
 		ka << reset->ka_shift;
 	val |= 1 << reset->reset_shift | 1 << reset->p_reset_shift;
@@ -282,7 +282,7 @@ static int pll_set_rate(struct iproc_clk *clk, unsigned int rate_index,
 
 	/* program integer part of NDIV */
 	val = readl(pll->pll_base + ctrl->ndiv_int.offset);
-	val &= ~(bit_mask(ctrl->ndiv_int.width) << ctrl->ndiv_int.shift);
+	val &= ~(GENAMSK(ctrl->ndiv_int.width - 1, 0) << ctrl->ndiv_int.shift);
 	val |= vco->ndiv_int << ctrl->ndiv_int.shift;
 	writel(val, pll->pll_base + ctrl->ndiv_int.offset);
 	if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK))
@@ -291,7 +291,7 @@ static int pll_set_rate(struct iproc_clk *clk, unsigned int rate_index,
 	/* program fractional part of NDIV */
 	if (ctrl->flags & IPROC_CLK_PLL_HAS_NDIV_FRAC) {
 		val = readl(pll->pll_base + ctrl->ndiv_frac.offset);
-		val &= ~(bit_mask(ctrl->ndiv_frac.width) <<
+		val &= ~(GENMASK(ctrl->ndiv_frac.width - 1, 0) <<
 			 ctrl->ndiv_frac.shift);
 		val |= vco->ndiv_frac << ctrl->ndiv_frac.shift;
 		writel(val, pll->pll_base + ctrl->ndiv_frac.offset);
@@ -301,7 +301,7 @@ static int pll_set_rate(struct iproc_clk *clk, unsigned int rate_index,
 
 	/* program PDIV */
 	val = readl(pll->pll_base + ctrl->pdiv.offset);
-	val &= ~(bit_mask(ctrl->pdiv.width) << ctrl->pdiv.shift);
+	val &= ~(GENMASK(ctrl->pdiv.width - 1, 0) << ctrl->pdiv.shift);
 	val |= vco->pdiv << ctrl->pdiv.shift;
 	writel(val, pll->pll_base + ctrl->pdiv.offset);
 	if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK))
@@ -365,13 +365,13 @@ static unsigned long iproc_pll_recalc_rate(struct clk_hw *hw,
 	 */
 	val = readl(pll->pll_base + ctrl->ndiv_int.offset);
 	ndiv_int = (val >> ctrl->ndiv_int.shift) &
-		bit_mask(ctrl->ndiv_int.width);
+		GENMASK(ctrl->ndiv_int.width - 1, 0);
 	ndiv = (u64)ndiv_int << ctrl->ndiv_int.shift;
 
 	if (ctrl->flags & IPROC_CLK_PLL_HAS_NDIV_FRAC) {
 		val = readl(pll->pll_base + ctrl->ndiv_frac.offset);
 		ndiv_frac = (val >> ctrl->ndiv_frac.shift) &
-			bit_mask(ctrl->ndiv_frac.width);
+			GENMASK(ctrl->ndiv_frac.width - 1, 0);
 
 		if (ndiv_frac != 0)
 			ndiv = ((u64)ndiv_int << ctrl->ndiv_int.shift) |
@@ -379,7 +379,7 @@ static unsigned long iproc_pll_recalc_rate(struct clk_hw *hw,
 	}
 
 	val = readl(pll->pll_base + ctrl->pdiv.offset);
-	pdiv = (val >> ctrl->pdiv.shift) & bit_mask(ctrl->pdiv.width);
+	pdiv = (val >> ctrl->pdiv.shift) & GENMASK(ctrl->pdiv.width - 1, 0);
 
 	clk->rate = (ndiv * parent_rate) >> ctrl->ndiv_int.shift;
 
@@ -487,7 +487,7 @@ static unsigned long iproc_clk_recalc_rate(struct clk_hw *hw,
 		return 0;
 
 	val = readl(pll->pll_base + ctrl->mdiv.offset);
-	mdiv = (val >> ctrl->mdiv.shift) & bit_mask(ctrl->mdiv.width);
+	mdiv = (val >> ctrl->mdiv.shift) & GENMASK(ctrl->mdiv.width - 1, 0);
 	if (mdiv == 0)
 		mdiv = 256;
 
@@ -534,12 +534,9 @@ static int iproc_clk_set_rate(struct clk_hw *hw, unsigned long rate,
 		return -EINVAL;
 
 	val = readl(pll->pll_base + ctrl->mdiv.offset);
-	if (div == 256) {
-		val &= ~(bit_mask(ctrl->mdiv.width) << ctrl->mdiv.shift);
-	} else {
-		val &= ~(bit_mask(ctrl->mdiv.width) << ctrl->mdiv.shift);
+	val &= ~(GENMASK(ctrl->mdiv.width - 1, 0) << ctrl->mdiv.shift);
+	if (div < 256)
 		val |= div << ctrl->mdiv.shift;
-	}
 	writel(val, pll->pll_base + ctrl->mdiv.offset);
 	if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK))
 		readl(pll->pll_base + ctrl->mdiv.offset);
diff --git a/drivers/clk/bcm/clk-iproc.h b/drivers/clk/bcm/clk-iproc.h
index d834b7a..5e4b66f 100644
--- a/drivers/clk/bcm/clk-iproc.h
+++ b/drivers/clk/bcm/clk-iproc.h
@@ -24,7 +24,6 @@
 
 #define IPROC_CLK_NAME_LEN 25
 #define IPROC_CLK_INVALID_OFFSET 0xffffffff
-#define bit_mask(width) ((1 << (width)) - 1)
 
 /* clocks that should not be disabled at runtime */
 #define IPROC_CLK_AON BIT(0)
diff --git a/drivers/clk/bcm/clk-kona-setup.c b/drivers/clk/bcm/clk-kona-setup.c
index deaa7f9..9397b54 100644
--- a/drivers/clk/bcm/clk-kona-setup.c
+++ b/drivers/clk/bcm/clk-kona-setup.c
@@ -307,7 +307,7 @@ static bool sel_valid(struct bcm_clk_sel *sel, const char *field_name,
 		 * in the array.
 		 */
 		max_sel = sel->parent_sel[sel->parent_count - 1];
-		limit = (1 << sel->width) - 1;
+		limit = GENMASK(sel->width - 1, 0);
 		if (max_sel > limit) {
 			pr_err("%s: bad selector for %s "
 					"(%u needs > %u bits)\n",
diff --git a/drivers/clk/bcm/clk-kona.c b/drivers/clk/bcm/clk-kona.c
index d9c039c..f5aa1cc 100644
--- a/drivers/clk/bcm/clk-kona.c
+++ b/drivers/clk/bcm/clk-kona.c
@@ -30,22 +30,16 @@
 
 /* Bitfield operations */
 
-/* Produces a mask of set bits covering a range of a 32-bit value */
-static inline u32 bitfield_mask(u32 shift, u32 width)
-{
-	return ((1 << width) - 1) << shift;
-}
-
 /* Extract the value of a bitfield found within a given register value */
 static inline u32 bitfield_extract(u32 reg_val, u32 shift, u32 width)
 {
-	return (reg_val & bitfield_mask(shift, width)) >> shift;
+	return (reg_val >> shift) & GENMASK(width - 1, 0);
 }
 
 /* Replace the value of a bitfield found within a given register value */
 static inline u32 bitfield_replace(u32 reg_val, u32 shift, u32 width, u32 val)
 {
-	u32 mask = bitfield_mask(shift, width);
+	u32 mask = GENMASK(width - 1, 0) << shift;
 
 	return (reg_val & ~mask) | (val << shift);
 }
@@ -94,7 +88,7 @@ u64 scaled_div_max(struct bcm_clk_div *div)
 	if (divider_is_fixed(div))
 		return (u64)div->u.fixed;
 
-	reg_div = ((u32)1 << div->u.s.width) - 1;
+	reg_div = GENMASK(div->u.s.width - 1, 0);
 
 	return scaled_div_value(div, reg_div);
 }
-- 
2.1.4

[PATCH v5 8/8] ARM: imx: switch to GENMASK()

[Andy Shevchenko]

Convert the code to use GENMASK() helper instead of div_mask() macro.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 drivers/clk/imx/clk-fixup-div.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/imx/clk-fixup-div.c b/drivers/clk/imx/clk-fixup-div.c
index 21db020..cd9a843 100644
--- a/drivers/clk/imx/clk-fixup-div.c
+++ b/drivers/clk/imx/clk-fixup-div.c
@@ -16,7 +16,6 @@
 #include "clk.h"
 
 #define to_clk_div(_hw) container_of(_hw, struct clk_divider, hw)
-#define div_mask(d)	((1 << (d->width)) - 1)
 
 /**
  * struct clk_fixup_div - imx integer fixup divider clock
@@ -70,13 +69,13 @@ static int clk_fixup_div_set_rate(struct clk_hw *hw, unsigned long rate,
 	/* Zero based divider */
 	value = divider - 1;
 
-	if (value > div_mask(div))
-		value = div_mask(div);
+	if (value > GENMASK(div->width - 1, 0))
+		value = GENMASK(div->width - 1, 0);
 
 	spin_lock_irqsave(div->lock, flags);
 
 	val = readl(div->reg);
-	val &= ~(div_mask(div) << div->shift);
+	val &= ~(GENMASK(div->width - 1, 0) << div->shift);
 	val |= value << div->shift;
 	fixup_div->fixup(&val);
 	writel(val, div->reg);
-- 
2.1.4

Re: [PATCH v5 3/8] clk: socfpga: switch to GENMASK()

[Dinh Nguyen]

On 07/13/2015 09:07 AM, Andy Shevchenko wrote:
> Convert the code to use GENMASK() helper instead of div_mask() macro.
> 
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> ---
>  drivers/clk/socfpga/clk-gate-a10.c   | 2 +-
>  drivers/clk/socfpga/clk-gate.c       | 2 +-
>  drivers/clk/socfpga/clk-periph-a10.c | 2 +-
>  drivers/clk/socfpga/clk-periph.c     | 2 +-
>  drivers/clk/socfpga/clk.h            | 1 -
>  5 files changed, 4 insertions(+), 5 deletions(-)
> 

Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>

Thanks,
Dinh

Re: [PATCH v5 1/8] clk: divider: switch to GENMASK()

[Stephen Boyd]

On 07/13, Andy Shevchenko wrote:
> Convert the code to use GENMASK() helper instead of div_mask() macro.
> 
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> ---
>  drivers/clk/clk-divider.c | 18 ++++++++----------
>  1 file changed, 8 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
> index 706b578..3bde790 100644
> --- a/drivers/clk/clk-divider.c
> +++ b/drivers/clk/clk-divider.c
> @@ -30,8 +30,6 @@
>  

#include <linux/bitops.h> ?

> @@ -391,10 +389,10 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
>  		spin_lock_irqsave(divider->lock, flags);
>  
>  	if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
> -		val = div_mask(divider->width) << (divider->shift + 16);
> +		val = GENMASK(divider->width - 1, 0) << (divider->shift + 16);
>  	} else {
>  		val = clk_readl(divider->reg);
> -		val &= ~(div_mask(divider->width) << divider->shift);
> +		val &= ~(GENMASK(divider->width - 1, 0) << divider->shift);

Shouldn't this be doing the shift in the GENMASK?

	start = divider->width - 1 + divider->shift;
	end = divider->shift;

	...

		val &= ~GENMASK(start, end);

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH v5 2/8] clk: mmp: switch to GENMASK()

[Stephen Boyd]

On 07/13, Andy Shevchenko wrote:
> diff --git a/drivers/clk/mmp/clk.h b/drivers/clk/mmp/clk.h
> index adf9b71..f5fdb0e 100644
> --- a/drivers/clk/mmp/clk.h
> +++ b/drivers/clk/mmp/clk.h
> @@ -39,7 +39,7 @@ extern struct clk *mmp_clk_register_factor(const char *name,
>  
>  /* Clock type "mix" */
>  #define MMP_CLK_BITS_MASK(width, shift)			\
> -		(((1 << (width)) - 1) << (shift))
> +		(GENMASK((width) - 1, 0) << (shift))

This can push the shift into the GENMASK instance too:

		(GENMASK((width) - 1 + (shift), (shift))

>  #define MMP_CLK_BITS_GET_VAL(data, width, shift)	\
>  		((data & MMP_CLK_BITS_MASK(width, shift)) >> (shift))
>  #define MMP_CLK_BITS_SET_VAL(val, width, shift)		\
> -- 
> 2.1.4
> 

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH v5 3/8] clk: socfpga: switch to GENMASK()

[Stephen Boyd]

On 07/13, Andy Shevchenko wrote:
> Convert the code to use GENMASK() helper instead of div_mask() macro.
> 
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> ---

Applied to clk-next

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH v5 1/8] clk: divider: switch to GENMASK()

[Andy Shevchenko]

On Tue, 2015-07-21 at 16:48 -0700, Stephen Boyd wrote:
> On 07/13, Andy Shevchenko wrote:
> > Convert the code to use GENMASK() helper instead of div_mask() 
> > macro.
> > 
> > Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> > ---
> >  drivers/clk/clk-divider.c | 18 ++++++++----------
> >  1 file changed, 8 insertions(+), 10 deletions(-)
> > 
> > diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
> > index 706b578..3bde790 100644
> > --- a/drivers/clk/clk-divider.c
> > +++ b/drivers/clk/clk-divider.c
> > @@ -30,8 +30,6 @@
> >  
> 
> #include <linux/bitops.h> ?

In clk-provider.h? It already is using BIT() macro. That's why I didn't
add the header inclusion.

> 
> > @@ -391,10 +389,10 @@ static int clk_divider_set_rate(struct clk_hw 
> > *hw, unsigned long rate,
> >  		spin_lock_irqsave(divider->lock, flags);
> >  
> >  	if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
> > -		val = div_mask(divider->width) << (divider->shift 
> > + 16);
> > +		val = GENMASK(divider->width - 1, 0) << (divider
> > ->shift + 16);
> >  	} else {
> >  		val = clk_readl(divider->reg);
> > -		val &= ~(div_mask(divider->width) << divider
> > ->shift);
> > +		val &= ~(GENMASK(divider->width - 1, 0) << divider
> > ->shift);
> 
> Shouldn't this be doing the shift in the GENMASK?

It shouldn't. I checked an assembly and it's far complex from the
proposed form.

> 
> 	start = divider->width - 1 + divider->shift;
> 	end = divider->shift;
> 
> 	...
> 
> 		val &= ~GENMASK(start, end);
> 

-- 
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel Finland Oy

Re: [PATCH v5 2/8] clk: mmp: switch to GENMASK()

[Andy Shevchenko]

On Tue, 2015-07-21 at 16:53 -0700, Stephen Boyd wrote:
> On 07/13, Andy Shevchenko wrote:
> > diff --git a/drivers/clk/mmp/clk.h b/drivers/clk/mmp/clk.h
> > index adf9b71..f5fdb0e 100644
> > --- a/drivers/clk/mmp/clk.h
> > +++ b/drivers/clk/mmp/clk.h
> > @@ -39,7 +39,7 @@ extern struct clk *mmp_clk_register_factor(const 
> > char *name,
> >  
> >  /* Clock type "mix" */
> >  #define MMP_CLK_BITS_MASK(width, shift)			\
> > -		(((1 << (width)) - 1) << (shift))
> > +		(GENMASK((width) - 1, 0) << (shift))
> 
> This can push the shift into the GENMASK instance too:

Too not optimal. I checked the assembly.

> 
> 		(GENMASK((width) - 1 + (shift), (shift))
> 
> >  #define MMP_CLK_BITS_GET_VAL(data, width, shift)	\
> >  		((data & MMP_CLK_BITS_MASK(width, shift)) >> 
> > (shift))
> >  #define MMP_CLK_BITS_SET_VAL(val, width, shift)		\
> > -- 
> > 2.1.4
> > 
> 

-- 
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel Finland Oy

Re: [PATCH v5 0/8] clk: replace div_mask() by GENMASK()

[Andy Shevchenko]

On Mon, 2015-07-13 at 17:07 +0300, Andy Shevchenko wrote:
> This series replaces div_mask() and similar macros in many clock 
> providers by
> GENMASK() generic helper.

So, if anyone finds this useful, please, ACK/apply.

> 
> Changelog v5:
>  - amend patch for softpga by covering all cases
>  - extend patchset to hisilicon and bcm clk implementation
>  - rebase on top of clk-next
> 
> Changelog v4:
>  - use GENMASK() instead of div_mask() by Stephen Boyd's comment
> 
> Changelog v3:
>  - fix clk_div_mask() prototype: seems tired like on Friday evening!
> 
> Changelog v2:
>  - fix patches 5,6,7 where parameter of the macro was d instead of d
> ->width
> 
> Andy Shevchenko (8):
>   clk: divider: switch to GENMASK()
>   clk: mmp: switch to GENMASK()
>   clk: socfpga: switch to GENMASK()
>   clk: ti: divider: switch to GENMASK()
>   clk: tegra: switch to GENMASK()
>   clk: hisilicon: switch to GENMASK()
>   clk: bcm: switch to GENMASK()
>   ARM: imx: switch to GENMASK()
> 
>  drivers/clk/bcm/clk-iproc-asiu.c          | 22 ++++++++-------------
> -
>  drivers/clk/bcm/clk-iproc-pll.c           | 31 ++++++++++++++-------
> ----------
>  drivers/clk/bcm/clk-iproc.h               |  1 -
>  drivers/clk/bcm/clk-kona-setup.c          |  2 +-
>  drivers/clk/bcm/clk-kona.c                | 12 +++---------
>  drivers/clk/clk-divider.c                 | 18 ++++++++----------
>  drivers/clk/hisilicon/clkdivider-hi6220.c |  8 +++-----
>  drivers/clk/imx/clk-fixup-div.c           |  7 +++----
>  drivers/clk/mmp/clk-mix.c                 |  2 +-
>  drivers/clk/mmp/clk.h                     |  2 +-
>  drivers/clk/socfpga/clk-gate-a10.c        |  2 +-
>  drivers/clk/socfpga/clk-gate.c            |  2 +-
>  drivers/clk/socfpga/clk-periph-a10.c      |  2 +-
>  drivers/clk/socfpga/clk-periph.c          |  2 +-
>  drivers/clk/socfpga/clk.h                 |  1 -
>  drivers/clk/tegra/clk-divider.c           |  7 +++----
>  drivers/clk/tegra/clk-pll.c               | 13 ++++++-------
>  drivers/clk/tegra/clk-super.c             |  2 +-
>  drivers/clk/ti/divider.c                  | 18 ++++++++----------
>  19 files changed, 64 insertions(+), 90 deletions(-)
> 

-- 
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel Finland Oy