From: Andi Kleen <andi@firstfloor.org>
To: peterz@infradead.org
Cc: linux-kernel@vger.kernel.org
Subject: perf: Some improvements for Skylake perf
Date: Thu, 15 Oct 2015 16:37:56 -0700 [thread overview]
Message-ID: <1444952280-24184-1-git-send-email-andi@firstfloor.org> (raw)
This patchkit improves the Skylake core PMU perf port
- Fix problems with LBR freezing with a new APIC ack sequence
- Improve performance and accuracy of the NMI handler with counter freezing
- Improve sampling quality with cycles:pp
The last feature could be used on other CPUs too, but for now it's only
enabled on Skylake.
-Andi
next reply other threads:[~2015-10-15 23:38 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-15 23:37 Andi Kleen [this message]
2015-10-15 23:37 ` [PATCH 1/4] x86, perf: Use a new PMU ack sequence on Skylake Andi Kleen
2015-10-16 11:51 ` Peter Zijlstra
2015-10-16 13:35 ` Andi Kleen
2015-10-16 15:00 ` Peter Zijlstra
2015-10-16 16:14 ` Mike Galbraith
2015-10-19 7:08 ` Ingo Molnar
2015-10-15 23:37 ` [PATCH 2/4] x86, perf: Factor out BTS enable/disable functions Andi Kleen
2015-10-15 23:37 ` [PATCH 3/4] perf, x86: Use counter freezing with Arch Perfmon v4 Andi Kleen
2015-10-15 23:38 ` [PATCH 4/4] x86, perf: Use INST_RETIRED.PREC_DIST for cycles:pp on Skylake Andi Kleen
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