From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753861AbbJTIJw (ORCPT ); Tue, 20 Oct 2015 04:09:52 -0400 Received: from mx0a-0016f401.pphosted.com ([67.231.148.174]:33219 "EHLO mx0a-0016f401.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753823AbbJTIJt (ORCPT ); Tue, 20 Oct 2015 04:09:49 -0400 From: Jisheng Zhang To: , , , , , , CC: , , Jisheng Zhang Subject: [PATCH 1/7] clocksource: arm_global_timer: fix ftrace Date: Tue, 20 Oct 2015 16:02:34 +0800 Message-ID: <1445328160-402-2-git-send-email-jszhang@marvell.com> X-Mailer: git-send-email 2.6.1 In-Reply-To: <1445328160-402-1-git-send-email-jszhang@marvell.com> References: <1445328160-402-1-git-send-email-jszhang@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2015-10-20_04:,, signatures=0 X-Proofpoint-Spam-Details: rule=inbound_notspam policy=inbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1507310000 definitions=main-1510200144 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Currently arm_global_timer can be used as a scheduler clock, we properly marked gt_sched_clock_read() as notrace. But we then call another function gt_counter_read() that _wasn't_ notrace. This patch fix this by adding an extra function to keep other users of gt_counter_read() traceable. Signed-off-by: Jisheng Zhang --- drivers/clocksource/arm_global_timer.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/clocksource/arm_global_timer.c b/drivers/clocksource/arm_global_timer.c index 29ea50a..a2cb6fa 100644 --- a/drivers/clocksource/arm_global_timer.c +++ b/drivers/clocksource/arm_global_timer.c @@ -60,7 +60,7 @@ static struct clock_event_device __percpu *gt_evt; * different to the 32-bit upper value read previously, go back to step 2. * Otherwise the 64-bit timer counter value is correct. */ -static u64 gt_counter_read(void) +static u64 notrace _gt_counter_read(void) { u64 counter; u32 lower; @@ -79,6 +79,11 @@ static u64 gt_counter_read(void) return counter; } +static u64 gt_counter_read(void) +{ + return _gt_counter_read(); +} + /** * To ensure that updates to comparator value register do not set the * Interrupt Status Register proceed as follows: @@ -201,7 +206,7 @@ static struct clocksource gt_clocksource = { #ifdef CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK static u64 notrace gt_sched_clock_read(void) { - return gt_counter_read(); + return _gt_counter_read(); } #endif -- 2.6.1