From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751306AbbKNNUi (ORCPT ); Sat, 14 Nov 2015 08:20:38 -0500 Received: from mail-pa0-f68.google.com ([209.85.220.68]:35933 "EHLO mail-pa0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751048AbbKNNUX (ORCPT ); Sat, 14 Nov 2015 08:20:23 -0500 From: Ranjith Thangavel To: gregkh@linuxfoundation.org Cc: abbotti@mev.co.uk, hsweeten@visionengravers.com, devel@driverdev.osuosl.org, linux-kernel@vger.kernel.org, ranjithece24@gmail.com Subject: [PATCH] comedi: pcmmio: Fix coding style - use BIT macro Date: Sat, 14 Nov 2015 18:54:04 +0530 Message-Id: <1447507444-11504-1-git-send-email-ranjithece24@gmail.com> X-Mailer: git-send-email 1.7.10.4 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org BIT macro is used for defining BIT location instead of shifting operator - coding style issue Signed-off-by: Ranjith Thangavel --- drivers/staging/comedi/drivers/pcmmio.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/staging/comedi/drivers/pcmmio.c b/drivers/staging/comedi/drivers/pcmmio.c index f7ec224..f2aedc21 100644 --- a/drivers/staging/comedi/drivers/pcmmio.c +++ b/drivers/staging/comedi/drivers/pcmmio.c @@ -84,20 +84,20 @@ #define PCMMIO_AI_LSB_REG 0x00 #define PCMMIO_AI_MSB_REG 0x01 #define PCMMIO_AI_CMD_REG 0x02 -#define PCMMIO_AI_CMD_SE BIT(7) +#define PCMMIO_AI_CMD_SE BIT(7) #define PCMMIO_AI_CMD_ODD_CHAN BIT(6) #define PCMMIO_AI_CMD_CHAN_SEL(x) (((x) & 0x3) << 4) #define PCMMIO_AI_CMD_RANGE(x) (((x) & 0x3) << 2) -#define PCMMIO_RESOURCE_REG 0x02 +#define PCMMIO_RESOURCE_REG 0x02 #define PCMMIO_RESOURCE_IRQ(x) (((x) & 0xf) << 0) #define PCMMIO_AI_STATUS_REG 0x03 #define PCMMIO_AI_STATUS_DATA_READY BIT(7) -#define PCMMIO_AI_STATUS_DATA_DMA_PEND BIT(6) -#define PCMMIO_AI_STATUS_CMD_DMA_PEND BIT(5) +#define PCMMIO_AI_STATUS_DATA_DMA_PEND BIT(6) +#define PCMMIO_AI_STATUS_CMD_DMA_PEND BIT(5) #define PCMMIO_AI_STATUS_IRQ_PEND BIT(4) -#define PCMMIO_AI_STATUS_DATA_DRQ_ENA BIT(2) +#define PCMMIO_AI_STATUS_DATA_DRQ_ENA BIT(2) #define PCMMIO_AI_STATUS_REG_SEL BIT(3) -#define PCMMIO_AI_STATUS_CMD_DRQ_ENA BIT(1) +#define PCMMIO_AI_STATUS_CMD_DRQ_ENA BIT(1) #define PCMMIO_AI_STATUS_IRQ_ENA BIT(0) #define PCMMIO_AI_RES_ENA_REG 0x03 #define PCMMIO_AI_RES_ENA_CMD_REG_ACCESS 0 @@ -126,12 +126,12 @@ #define PCMMIO_AO_CMD_CHAN_SEL_ALL (0x0f << 0) #define PCMMIO_AO_STATUS_REG 0x0b #define PCMMIO_AO_STATUS_DATA_READY BIT(7) -#define PCMMIO_AO_STATUS_DATA_DMA_PEND BIT(6) -#define PCMMIO_AO_STATUS_CMD_DMA_PEND BIT(5) +#define PCMMIO_AO_STATUS_DATA_DMA_PEND BIT(6) +#define PCMMIO_AO_STATUS_CMD_DMA_PEND BIT(5) #define PCMMIO_AO_STATUS_IRQ_PEND BIT(4) -#define PCMMIO_AO_STATUS_DATA_DRQ_ENA BIT(2) +#define PCMMIO_AO_STATUS_DATA_DRQ_ENA BIT(2) #define PCMMIO_AO_STATUS_REG_SEL BIT(3) -#define PCMMIO_AO_STATUS_CMD_DRQ_ENA BIT(1) +#define PCMMIO_AO_STATUS_CMD_DRQ_ENA BIT(1) #define PCMMIO_AO_STATUS_IRQ_ENA BIT(0) #define PCMMIO_AO_RESOURCE_ENA_REG 0x0b #define PCMMIO_AO_2ND_DAC_OFFSET 0x04 -- 1.7.10.4