From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965334AbbLWUaT (ORCPT ); Wed, 23 Dec 2015 15:30:19 -0500 Received: from mail-wm0-f41.google.com ([74.125.82.41]:33848 "EHLO mail-wm0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754875AbbLWUaP (ORCPT ); Wed, 23 Dec 2015 15:30:15 -0500 From: Carlos Soto To: Shawn Guo , Sascha Hauer , Michael Turquette , Stephen Boyd , linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Carlos Soto Subject: [PATCH 1/1] imx25: Fix LCD pixelclock configuration Date: Wed, 23 Dec 2015 21:30:10 +0100 Message-Id: <1450902610-27224-1-git-send-email-csotoalonso@gmail.com> X-Mailer: git-send-email 1.7.10.4 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Set LCDC base clock (per_7) parent clock to UPLL clock. This is needed to allow finer resolution in pixelclock Signed-off-by: Carlos Soto --- drivers/clk/imx/clk-imx25.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/clk/imx/clk-imx25.c b/drivers/clk/imx/clk-imx25.c index c4c141c..656340e 100644 --- a/drivers/clk/imx/clk-imx25.c +++ b/drivers/clk/imx/clk-imx25.c @@ -238,6 +238,12 @@ static int __init __mx25_clocks_init(unsigned long osc_rate, clk_set_parent(clk[per5_sel], clk[ahb]); /* + * set LCDC base clock (per 7) to highest possible frequency (UPLL) + * to get best resolution for pixel clock + */ + clk_set_parent(clk[per7_sel], clk[upll]); + + /* * Let's initially set up CLKO parent as ipg, since this configuration * is used on some imx25 board designs to clock the audio codec. */ -- 1.7.10.4