From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753096AbcADEbl (ORCPT ); Sun, 3 Jan 2016 23:31:41 -0500 Received: from arroyo.ext.ti.com ([192.94.94.40]:47698 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752811AbcADE2e (ORCPT ); Sun, 3 Jan 2016 23:28:34 -0500 From: Milo Kim To: CC: , , , , , , , Milo Kim Subject: [PATCH 08/19] irqchip: atmel-aic: add common mask and unmask functions Date: Mon, 4 Jan 2016 13:28:32 +0900 Message-ID: <1451881723-2478-9-git-send-email-milo.kim@ti.com> X-Mailer: git-send-email 2.6.4 In-Reply-To: <1451881723-2478-1-git-send-email-milo.kim@ti.com> References: <1451881723-2478-1-git-send-email-milo.kim@ti.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org AIC has one register access to enable/disable an interrupt. AIC5 requires two register accesses - SSR and IECR/IDCR. This patch unifies interrupt mask and unmask operations. Mask and unmask operations are moved into aic_common_of_init(). AIC5 can have multiple IRQ chips, mask/unmask should be assigned per chip. In case of AIC, it's also good because AIC has one IRQ chip. So looping count is just one time to configure mask/unmask functions. struct irq_domain *__init aic_common_of_init(struct device_node *node, const char *name, int nirqs) { ... for (i = 0; i < nchips; i++) { gc = irq_get_domain_generic_chip(domain, i * AIC_IRQS_PER_CHIP); ... gc->chip_types[0].chip.irq_mask = aic_mask; gc->chip_types[0].chip.irq_unmask = aic_unmask; gc->private = &aic[i]; } } In AIC, register configuration for enabling and disabling IRQ can be replaced with irq_mask and irq_unmask. This is for using unified mask and unmask functions (aic_mask and aic_unmask). Cc: Thomas Gleixner Cc: Jason Cooper Cc: Marc Zyngier Cc: Alexandre Belloni Cc: Boris BREZILLON Cc: Ludovic Desroches Cc: Nicolas Ferre Cc: linux-kernel@vger.kernel.org Signed-off-by: Milo Kim --- drivers/irqchip/irq-atmel-aic-common.c | 52 ++++++++++++++++++++++++++++++++++ drivers/irqchip/irq-atmel-aic.c | 4 --- drivers/irqchip/irq-atmel-aic5.c | 36 ----------------------- 3 files changed, 52 insertions(+), 40 deletions(-) diff --git a/drivers/irqchip/irq-atmel-aic-common.c b/drivers/irqchip/irq-atmel-aic-common.c index 94c9dad..533b3e9 100644 --- a/drivers/irqchip/irq-atmel-aic-common.c +++ b/drivers/irqchip/irq-atmel-aic-common.c @@ -193,6 +193,56 @@ static void aic_common_shutdown(struct irq_data *d) ct->chip.irq_mask(d); } +static void aic_mask(struct irq_data *d) +{ + struct irq_domain *domain = d->domain; + struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0); + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + u32 mask = d->mask; + + /* + * Disable interrupt. We always take the lock of the + * first irq chip as all chips share the same registers. + */ + irq_gc_lock(bgc); + + if (aic_is_ssr_used()) { + irq_reg_writel(gc, d->hwirq, aic_reg_data->ssr); + irq_reg_writel(gc, 1, aic_reg_data->idcr); + } else { + irq_reg_writel(gc, mask, aic_reg_data->idcr); + } + + gc->mask_cache &= ~mask; + + irq_gc_unlock(bgc); +} + +static void aic_unmask(struct irq_data *d) +{ + struct irq_domain *domain = d->domain; + struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0); + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + u32 mask = d->mask; + + /* + * Enable interrupt. We always take the lock of the + * first irq chip as all chips share the same registers. + */ + irq_gc_lock(bgc); + + if (aic_is_ssr_used()) { + irq_reg_writel(gc, d->hwirq, aic_reg_data->ssr); + irq_reg_writel(gc, 1, aic_reg_data->iecr); + } else { + irq_reg_writel(gc, mask, aic_reg_data->iecr); + } + + gc->mask_cache |= mask; + + irq_gc_unlock(bgc); +} + int aic_common_set_type(struct irq_data *d, unsigned type, unsigned *val) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); @@ -303,6 +353,8 @@ struct irq_domain *__init aic_common_of_init(struct device_node *node, gc->chip_types[0].chip.irq_eoi = irq_gc_eoi; gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake; gc->chip_types[0].chip.irq_shutdown = aic_common_shutdown; + gc->chip_types[0].chip.irq_mask = aic_mask; + gc->chip_types[0].chip.irq_unmask = aic_unmask; gc->private = &aic[i]; } diff --git a/drivers/irqchip/irq-atmel-aic.c b/drivers/irqchip/irq-atmel-aic.c index 46ce3ca..df12249d 100644 --- a/drivers/irqchip/irq-atmel-aic.c +++ b/drivers/irqchip/irq-atmel-aic.c @@ -185,10 +185,6 @@ static int __init aic_of_init(struct device_node *node, gc = irq_get_domain_generic_chip(domain, 0); gc->chip_types[0].regs.eoi = AT91_AIC_EOICR; - gc->chip_types[0].regs.enable = AT91_AIC_IECR; - gc->chip_types[0].regs.disable = AT91_AIC_IDCR; - gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg; - gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg; gc->chip_types[0].chip.irq_retrigger = aic_retrigger; gc->chip_types[0].chip.irq_set_type = aic_set_type; gc->chip_types[0].chip.irq_suspend = aic_suspend; diff --git a/drivers/irqchip/irq-atmel-aic5.c b/drivers/irqchip/irq-atmel-aic5.c index ecaa7e0..e610780 100644 --- a/drivers/irqchip/irq-atmel-aic5.c +++ b/drivers/irqchip/irq-atmel-aic5.c @@ -83,40 +83,6 @@ aic5_handle(struct pt_regs *regs) handle_domain_irq(aic5_domain, irqnr, regs); } -static void aic5_mask(struct irq_data *d) -{ - struct irq_domain *domain = d->domain; - struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0); - struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); - - /* - * Disable interrupt on AIC5. We always take the lock of the - * first irq chip as all chips share the same registers. - */ - irq_gc_lock(bgc); - irq_reg_writel(gc, d->hwirq, AT91_AIC5_SSR); - irq_reg_writel(gc, 1, AT91_AIC5_IDCR); - gc->mask_cache &= ~d->mask; - irq_gc_unlock(bgc); -} - -static void aic5_unmask(struct irq_data *d) -{ - struct irq_domain *domain = d->domain; - struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0); - struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); - - /* - * Enable interrupt on AIC5. We always take the lock of the - * first irq chip as all chips share the same registers. - */ - irq_gc_lock(bgc); - irq_reg_writel(gc, d->hwirq, AT91_AIC5_SSR); - irq_reg_writel(gc, 1, AT91_AIC5_IECR); - gc->mask_cache |= d->mask; - irq_gc_unlock(bgc); -} - static int aic5_retrigger(struct irq_data *d) { struct irq_domain *domain = d->domain; @@ -273,8 +239,6 @@ static int __init aic5_of_init(struct device_node *node, gc = irq_get_domain_generic_chip(domain, i * AIC_IRQS_PER_CHIP); gc->chip_types[0].regs.eoi = AT91_AIC5_EOICR; - gc->chip_types[0].chip.irq_mask = aic5_mask; - gc->chip_types[0].chip.irq_unmask = aic5_unmask; gc->chip_types[0].chip.irq_retrigger = aic5_retrigger; gc->chip_types[0].chip.irq_set_type = aic5_set_type; gc->chip_types[0].chip.irq_suspend = aic5_suspend; -- 2.6.4