From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755644AbcAHOMl (ORCPT ); Fri, 8 Jan 2016 09:12:41 -0500 Received: from szxga01-in.huawei.com ([58.251.152.64]:29590 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755183AbcAHODT (ORCPT ); Fri, 8 Jan 2016 09:03:19 -0500 From: John Garry To: , , , , , , CC: , , , , , , , , John Garry Subject: [PATCH 01/23] devicetree: bindings: hisi_sas: add v2 HW bindings Date: Fri, 8 Jan 2016 22:15:20 +0800 Message-ID: <1452262542-64589-2-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1452262542-64589-1-git-send-email-john.garry@huawei.com> References: <1452262542-64589-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020204.568FC1A1.012C,ss=1,re=0.000,recu=0.000,reip=0.000,cl=1,cld=1,fgs=0, ip=0.0.0.0, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 51c60080ae19b1141c7effb20d061870 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the dt bindings for HiSi SAS controller v2 HW. The main difference in the controllers from dt perspective is interrupts. Signed-off-by: John Garry --- .../devicetree/bindings/scsi/hisilicon-sas.txt | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt b/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt index 0a7a325..2695023 100644 --- a/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt +++ b/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt @@ -5,6 +5,7 @@ The HiSilicon SAS controller supports SAS/SATA. Main node required properties: - compatible : value should be as follows: (a) "hisilicon,hip05-sas-v1" for v1 hw in hip05 chipset + (b) "hisilicon,hip06-sas-v2" for v2 hw in hip06 chipset - sas-addr : array of 8 bytes for host SAS address - reg : Address and length of the SAS register - hisilicon,sas-syscon: phandle of syscon used for sas control @@ -13,11 +14,11 @@ Main node required properties: - ctrl-clock-ena-reg : offset to controller clock enable register in ctrl reg - queue-count : number of delivery and completion queues in the controller - phy-count : number of phys accessible by the controller - - interrupts : Interrupts for phys, completion queues, and fatal + - interrupts : For v1 hw: Interrupts for phys, completion queues, and fatal sources; the interrupts are ordered in 3 groups, as follows: - - Phy interrupts - - Completion queue interrupts - - Fatal interrupts + - Phy interrupts + - Completion queue interrupts + - Fatal interrupts Phy interrupts : Each phy has 3 interrupt sources: - broadcast - phyup @@ -25,11 +26,28 @@ Main node required properties: The phy interrupts are ordered into groups of 3 per phy (broadcast, phyup, and abnormal) in increasing order. Completion queue interrupts : each completion queue has 1 - interrupt source. - The interrupts are ordered in increasing order. + interrupt source. The interrupts are ordered in + increasing order. Fatal interrupts : the fatal interrupts are ordered as follows: - ECC - AXI bus + For v2 hw: Interrupts for phys, Sata, and completion queues; + the interrupts are ordered in 3 groups, as follows: + - Phy interrupts + - Sata interrupts + - Completion queue interrupts + Phy interrupts : Each controller has 2 phy interrupts: + - phy up/down + - channel interrupt + Sata interrupts : Each phy on the controller has 1 Sata + interrupt. The interrupts are ordered in increasing + order. + Completion queue interrupts : each completion queue has 1 + interrupt source. The interrupts are ordered in + increasing order. + +Optional main node properties: + - am-max-trans : limit controller for am max transmissions Example: sas0: sas@c1000000 { -- 1.9.1