From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756487AbcAMO1w (ORCPT ); Wed, 13 Jan 2016 09:27:52 -0500 Received: from mail-sn1nam02on0063.outbound.protection.outlook.com ([104.47.36.63]:58640 "EHLO NAM02-SN1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751194AbcAMO1t (ORCPT ); Wed, 13 Jan 2016 09:27:49 -0500 X-Greylist: delayed 857 seconds by postgrey-1.27 at vger.kernel.org; Wed, 13 Jan 2016 09:27:49 EST Authentication-Results: spf=pass (sender IP is 149.199.60.83) smtp.mailfrom=xilinx.com; vger.kernel.org; dkim=none (message not signed) header.d=none;vger.kernel.org; dmarc=bestguesspass action=none header.from=xilinx.com; From: Subbaraya Sundeep Bhatta To: , CC: , , , , "Subbaraya Sundeep Bhatta" Subject: [PATCH v2 2/3] phy: zynqmp: Add dt bindings for ZynqMP PHY. Date: Wed, 13 Jan 2016 19:43:24 +0530 Message-ID: <1452694404-1253-1-git-send-email-sbhatta@xilinx.com> X-Mailer: git-send-email 2.1.2 X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.0.0.1202-22060.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:149.199.60.83;CTRY:US;IPV:NLI;EFV:NLI;SFV:NSPM;SFS:(10009020)(6009001)(2980300002)(438002)(189002)(199003)(47776003)(1220700001)(50986999)(11100500001)(106466001)(90966002)(189998001)(19580405001)(33646002)(42186005)(4001430100002)(586003)(48376002)(63266004)(36386004)(103686003)(5008740100001)(81156007)(2906002)(5003940100001)(36756003)(575784001)(4326007)(107886002)(50226001)(229853001)(52956003)(87936001)(1096002)(45336002)(6806005)(5001770100001)(46386002)(92566002)(19580395003)(50466002)(5001960100002)(86362001)(107986001);DIR:OUT;SFP:1101;SCL:1;SRVR:SN1NAM02HT169;H:xsj-pvapsmtpgw01;FPR:;SPF:Pass;PTR:unknown-60-83.xilinx.com;MX:1;A:1;LANG:en; MIME-Version: 1.0 Content-Type: text/plain X-MS-Office365-Filtering-Correlation-Id: 4ec69fb1-a5e6-4438-a347-08d31c23b71f X-Exchange-Antispam-Report-Test: UriScan:;BCL:0;PCL:0;RULEID:(8251501002);SRVR:SN1NAM02HT169;UriScan:(192813158149592); X-Microsoft-Antispam-PRVS: <16ab415cc846407d97b934cae17968d8@SN1NAM02HT169.eop-nam02.prod.protection.outlook.com> X-Exchange-Antispam-Report-CFA-Test: BCL:0;PCL:0;RULEID:(601004)(2401047)(13015025)(13017025)(520078)(13018025)(5005006)(8121501046)(3002001)(10201501046);SRVR:SN1NAM02HT169;BCL:0;PCL:0;RULEID:;SRVR:SN1NAM02HT169; X-Forefront-PRVS: 08200063E9 X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jan 2016 14:13:30.7983 (UTC) X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.83];Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN1NAM02HT169 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds the document describing dt bindings for ZynqMP PHY. ZynqMP SOC has a High Speed Processing System Gigabit Transceiver which provides PHY capabilties to USB, SATA, PCIE, Display Port and Ehernet SGMII controllers. Signed-off-by: Subbaraya Sundeep Bhatta --- v2: modified to use phy cells as 2. .../devicetree/bindings/phy/phy-zynqmp.txt | 103 +++++++++++++++++++++ 1 file changed, 103 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-zynqmp.txt diff --git a/Documentation/devicetree/bindings/phy/phy-zynqmp.txt b/Documentation/devicetree/bindings/phy/phy-zynqmp.txt new file mode 100644 index 0000000..975cf21 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-zynqmp.txt @@ -0,0 +1,103 @@ +Xilinx ZynqMP PHY binding + +This binding describes a ZynqMP PHY device that is used to control ZynqMP +High Speed Gigabit Transceiver(GT). ZynqMP PS GTR provides four lanes +and are used by USB, SATA, PCIE, Display port and Ethernet SGMMI controllers. + +Required properties (controller (parent) node): +- compatible : Should be "xlnx,zynqmp-psgtr" + +- reg : Address and length of register sets for each device in + "reg-names" +- reg-names : The names of the register addresses corresponding to the + registers filled in "reg": + - serdes: SERDES block register set + - siou: SIOU block register set + - lpd: Low power domain peripherals reset control + - fpd: Full power domain peripherals reset control + +-xlnx,tx_termination_fix: Include fix for a functional issue in the GT. The TX + termination resistance can be out of spec due to a + bug in the calibration logic. This issue will be fixed + in silicon in future versions. + +Required nodes : A sub-node is required for each lane the controller + provides. + +Required properties (port (child) nodes): +lane0: +- #phy-cells : Should be 2 + Cell after port phandle is device type from: + - + - + - + - + - +lane1: +- #phy-cells : Should be 2 + Cell after port phandle is device type from: + - + - + - + - + - +lane2: +- #phy-cells : Should be 2 + Cell after port phandle is device type from: + - + - + - + - + - +lane3: +- #phy-cells : Should be 2 + Cell after port phandle is device type from: + - + - + - + - + - + +Example: + zynqmp_phy@fd400000 { + compatible = "xlnx,zynqmp-psgtr"; + status = "okay"; + reg = <0x0 0xfd400000 0x40000>, <0x0 0xfd3d0000 0x1000>, + <0x0 0xfd1a0000 0x1000>, <0x0 0xff5e0000 0x1000>; + reg-names = "serdes", "siou", "fpd", "lpd"; + + lane0: lane@0 { + #phy-cells = <2>; + }; + lane1: lane@1 { + #phy-cells = <2>; + }; + lane2: lane@2 { + #phy-cells = <2>; + }; + lane3: lane@3 { + #phy-cells = <2>; + }; + }; + +Specifying phy control of devices +================================= + +Device nodes should specify the configuration required in their "phys" +property, containing a phandle to the phy port node and a device type. + +Example: + +#include + + usb@fe200000 { + ... + phys = <&lane2 PHY_TYPE_USB3 0>; + ... + }; + + ahci@fd0c0000 { + ... + phys = <&lane3 PHY_TYPE_SATA 1>; + ... + }; -- 2.1.2