From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752725AbcAMPtJ (ORCPT ); Wed, 13 Jan 2016 10:49:09 -0500 Received: from mail.skyhub.de ([78.46.96.112]:56792 "EHLO mail.skyhub.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752555AbcAMPtH (ORCPT ); Wed, 13 Jan 2016 10:49:07 -0500 From: Borislav Petkov To: Jonathan Corbet Cc: Eric Morton , linux-doc@vger.kernel.org, LKML Subject: [PATCH] Documentation: Explain pci=conf1,conf2 more verbosely Date: Wed, 13 Jan 2016 16:48:51 +0100 Message-Id: <1452700131-17557-1-git-send-email-bp@alien8.de> X-Mailer: git-send-email 2.3.5 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Borislav Petkov People complained that setting the PCI config space access mechanism through "pci=conf1" or "pci=conf2" on the command line is not really documented. Yeah, can you blame them? Look at what we have now. So try to improve the situation a bit by explaining what those "conf1" and "conf2" things actually mean. See http://wiki.osdev.org/PCI for more info. Suggested-by: Eric Morton Signed-off-by: Borislav Petkov --- Documentation/kernel-parameters.txt | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt index 742f69d18fc8..d1f5e057f3f3 100644 --- a/Documentation/kernel-parameters.txt +++ b/Documentation/kernel-parameters.txt @@ -2733,10 +2733,14 @@ bytes respectively. Such letter suffixes can also be entirely omitted. hardware access methods are allowed. Use this if you experience crashes upon bootup and you suspect they are caused by the BIOS. - conf1 [X86] Force use of PCI Configuration - Mechanism 1. - conf2 [X86] Force use of PCI Configuration - Mechanism 2. + conf1 [X86] Force use of PCI Configuration Access + Mechanism 1 (config address in IO port 0xCF8, + data in IO port 0xCFC, both 32-bit). + conf2 [X86] Force use of PCI Configuration Access + Mechanism 2 (IO port 0xCF8 is an 8-bit port for + the function, IO port 0xCFA, also 8-bit, sets + bus number. The config space is then accessed + through ports 0xC000-0xCFFF). noaer [PCIE] If the PCIEAER kernel config parameter is enabled, this kernel boot option can be used to disable the use of PCIE advanced error reporting. -- 2.3.5