From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754099AbcANAMd (ORCPT ); Wed, 13 Jan 2016 19:12:33 -0500 Received: from gate.crashing.org ([63.228.1.57]:58870 "EHLO gate.crashing.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754025AbcANAMc (ORCPT ); Wed, 13 Jan 2016 19:12:32 -0500 Message-ID: <1452727756.2403.47.camel@kernel.crashing.org> Subject: Re: [PATCH v1 3/3] ARM64 LPC: update binding doc From: Benjamin Herrenschmidt To: Rongrong Zou , arnd@arndb.de, catalin.marinas@arm.com, will.deacon@arm.com Cc: lijianhua@huawei.com, lixiancai@huawei.com, linuxarm@huawei.com, linux-kernel@vger.kernel.org, minyard@acm.org, gregkh@linuxfoundation.org Date: Thu, 14 Jan 2016 10:29:16 +1100 In-Reply-To: <1451396032-23708-4-git-send-email-zourongrong@gmail.com> References: <1451396032-23708-1-git-send-email-zourongrong@gmail.com> <1451396032-23708-4-git-send-email-zourongrong@gmail.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.18.3 (3.18.3-1.fc23) Mime-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 2015-12-29 at 21:33 +0800, Rongrong Zou wrote: > Signed-off-by: Rongrong Zou > --- >  .../devicetree/bindings/arm64/low-pin-count.txt      | 20 ++++++++++++++++++++ >  1 file changed, 20 insertions(+) >  create mode 100644 Documentation/devicetree/bindings/arm64/low-pin-count.txt > > diff --git a/Documentation/devicetree/bindings/arm64/low-pin-count.txt b/Documentation/devicetree/bindings/arm64/low-pin-count.txt > new file mode 100644 > index 0000000..215f2c4 > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm64/low-pin-count.txt > @@ -0,0 +1,20 @@ > +Low Pin Count bus driver > + > +Usually LPC controller is part of PCI host bridge, so the legacy ISA > +port locate on LPC bus can be accessed directly. But some SoC have > +independent LPC controller, and we can access the legacy port by specifying > +LPC address cycle. Thus, LPC driver is introduced. > + > +Required properties: > +- compatible: "low-pin-count" I'm not sure about the above. I'd rather just make it "isa" or maybe isa-lpc. The LPC bus is fundamentally an ISA bus with the 3 cycle types of ISA etc... I would also allow the node to be named "isa". > +- reg: specifies low pin count address range > + > + > +Example: > + > +        lpc_0: lpc@a01b0000 { > + #address-cells = <1>; > + #size-cells = <1>; As discussed earlier, address-cells should be 2 with the first cell indicating the address space type (0 = mem, 1 = IO, possibly 2 = firmware but that remains somewhat TBD).   > +                compatible = "low-pin-count"; > +                reg = <0x0 0xa01b0000 0x0 0x10000>; And also as discussed, this is the business of the "ranges" property so that children devices can be properly expressed. > +        }; Also, this being a bus binding, it should describe the format for children (for example, PNP related properties). That leads to the obvious question: Why not just reference the existing Open Firmware ISA binding ? Cheers, Ben.